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stpc ? atlas x86 core pc compatible system-on-chip for terminals issue 1.0 - july 24, 2002 1/111 figure 0-1. logic diagram n powerful x86 processor n 64-bit sdram uma controller n graphics controller - vga & svga crt controller - 135mhz ramdac - enhanced 2d graphics engine n video input port n video pipeline - up-scaler - video colour space converter - chroma & colour key support n tft display controller n pci 2.1 master / slave / arbiter n isa master / slave controller n 16-bit local bus interface n pcmcia interface controller n eide controller n 2 usb host hub interfaces n i/o features - pc/at+ keyboard controller - ps/2 mouse controller - 2 serial ports - 1 parallel port - 16 general purpose i/os - i2c interface n integrated peripheral controller - dma controller - interrupt controller - timer / counters n power management unit n watchdog n jtag ieee1149.1 pbga516 s t p c a t l a s x86 core host i/f sdram ctrl svga ge i/f vip pci m/s lb ctrl pci bus isa m/s ipc pci m/s isa bus crtc cursor monitor ide i/f pmu wdog video pipeline c key k key lut local bus pcmcia i/os usb tft tft i/f video in
stpc ? atlas 2/111 issue 1.0 - jul y 24, 2002 description the stpc atlas integrates a standard 5th generation x86 core along with a powerful uma graphics/video chipset, support logic including pci, isa, local bus, usb, eide controllers and combines them with standard i/o interfaces to provide a single pc compatible subsystem on a single device, suitable for all kinds of terminal and industrial appliances. n x86 processor core n fully static 32-bit 5-stage pipeline, x86 processor fully pc compatible. n can access up to 4gb of external memory. n 8kbyte unified instruction and data cache with write back and write through capability. n parallel processing integral floating point unit, with automatic power down. n runs up to 133 mhz (x2). n fully static design for dynamic clock control. n low power and system management modes. n optimized design for 2.5v operation. n sdram controller n 64-bit data bus. n up to 90mhz sdram clock speed. n integrated system memory, graphic frame memory and video frame memory. n supports 8mb up to 128 mb system memory. n supports 16-mbit, 64-mbit and 128-mbit sdrams. n supports 8, 16, 32, 64, and 128 mb dimms. n supports buffered, non buffered, and registered dimms n 4-line write buffers for cpu to dram and pci to dram cycles. n 4-line read prefetch buffers for pci masters. n programmable latency n programmable timing for sdram parameters. n supports -8, -10, -12, -13, -15 memory parts n supports memory hole between 1mb and 8mb for pci/isa busses. n 32-bit access, autoprecharge & power-down are not supported. n enhanced 2d graphics controller n supports pixel depths of 8, 16, 24 and 32 bit. n full bitblt implementation for all 256 raster operations defined for windows. n supports 4 transparent blt modes - bitmap transparency, pattern transparency, source transparency and destination transparency. n hardware clipping n fast line draw engine with anti-aliasing. n supports 4-bit alpha blended font for anti- aliased text display. n complete double buffered registers for pipelined operation. n 64-bit wide pipelined architecture running at 90 mhz. hardware clipping n crt controller n integrated 135mhz triple ramdac allowing for 1280 x 1024 x 75hz display. n 8-, 16-, 24-bit pixels. n interlaced or non-interlaced output. n video input port n accepts video inputs in ccir 601/656 mode. n optional 2:1 decimator n stores captured video in off setting area of the onboard frame buffer. n hsync and b/t generation or lock onto external video timing source. n video pipeline n two-tap interpolative horizontal filter. n two-tap interpolative vertical filter. n color space conversion (rgb to yuv and yuv to rgb). n programmable window size. n chroma and color keying for integrated video overlay.
stpc ? atlas issue 1.0 - july 24, 2002 3/111 n tft interface n programmable panel size up to 1024 by 1024 pixels. n support for vga and svga active matrix tft flat panels with 9, 12, 18-bit interface (1 pixel per clock). n support for xga and sxga active matrix tft flat panels with 2 x 9-bit interface (2 pixels per clock). n programmable image positionning. n programmable blank space insertion in text mode. n programmable horizontal and vertical image expansion in graphic mode. n one fully programmable pwm (pulse width modulator) signals to adjust the flat panel brightness and contrast. n supports panellink tm high speed serial transmitter externally for high resolution panel interface. n pci controller n compatible with pci 2.1 specification. n integrated pci arbitration interface. up to 3 masters can connect directly. external logic allows for greater than 3 masters. n translation of pci cycles to isa bus. n translation of isa master initiated cycle to pci. n support for burst read/write from pci master. n pci clock is 1/2, 1/3 or 1/4 host bus clock. n isa master/slave n generates the isa clock from either 14.318mhz oscillator clock or pci clock n supports programmable extra wait state for isa cycles n supports i/o recovery time for back to back i/o cycles. n fast gate a20 and fast reset. n supports the single rom that c, d, or e. blocks shares with f block bios rom. n supports flash rom. n supports isa hidden refresh. n buffered dma & isa master cycles to reduce bandwidth utilization of the pci and host bus. n local bus interface n multiplexed with isa/dma interface. n low latency asynchronous bus n 16-bit data bus with word steering capability. n programmable timing (host clock granularity) n 4 programmable flash chip select. n 8 programmable i/o chip select. n i/o device timing (setup & recovery time) programmable n supports 32-bit flash burst. n 2-level hardware key protection for flash boot block protection. n supports 2 banks of 32mb flash devices with boot block shadowed to 0x000f0000. n reallocatable memory space windows n eide interface n supports pio n transfer rates to 22 mbytes/sec n supports up to 4 ide devices n concurrent channel operation (pio modes) - 4 x 32-bit buffer fifos per channel n support for pio mode 3 & 4. n individual drive timing for all four ide devices n supports both legacy & native ide modes n supports hard drives larger than 528mb n support for cd-rom and tape peripherals n backward compatibility with ide (ata-1). n integrated peripheral controller n 2x8237/at compatible 7-channel dma controller. n 2x8259/at compatible interrupt controller. 16 interrupt inputs - isa and pci. n three 8254 compatible timer/counters. n co-processor error support logic. n supports external rtc (not in local bus mode).
stpc ? atlas 4/111 issue 1.0 - jul y 24, 2002 n pcmcia interface n support one pcmcia 68-pin standard pc card socket. n power management support. n support pcmcia/ata specifications. n support i/o pc card with pulse-mode interrupts. n usb interface n usb 1.1 compatible. n open hci 1.0 compliant. n user configurable roothub. n support for both lowspeed and highspeed usb devices. n no bi-directionnal or tri-state busses. n no level sensitive latches. n system management interrupt pin support n hooks for legacy device support. n keyboard interface n fully pc/at+ compatible n mouse interface n fully ps/2 compatible n serial interface n 15540 compatible n programmable word length, stop bits, parity. n 16-bit programmable baud rate generator. n interrupt generator. n loop-back mode. n 8-bit scratch register. n two 16-bit fifos. n two dma handshake lines. parallel port n all ieee standard 1284 protocols supported: compatibility, nibble, byte, epp, and ecp modes. n 16 bytes fifo for ecp. n power management n four power saving modes: on, doze, standby, suspend. n programmable system activity detector n supports intel & cyrix smm and apm. n supports stopclk. n supports io trap & restart. n independent peripheral time-out timer to monitor hard disk, serial & parallel port. n 128k sm_ram address space from 0xa0000 to 0xb0000 n jtag n boundary scan compatible ieee1149.1. n scan chain control. n bypass register compatible ieee1149.1. n id register compatible ieee1149.1. n ram bist control. . exca is a trademark of pcmcia / jeida. panellink is a trademark of siliconimage, inc
general description issue 1.0 - july 24, 2002 5/111 1. general description at the heart of the stpc atlas is an advanced processor block that includes a powerful x86 processor core along with a 64-bit sdram controller, advanced 64-bit accelerated graphics and video controller, a high speed pci bus controller and industry standard pc chip set functions (interrupt controller, dma controller, interval timer and isa bus). the stpc atlas has in addition, a tft output, a video input, an eide controller, a local bus interface, pcmcia and super i/o features including usb host hub. 1.1. architecture the stpc atlas makes use of a tightly coupled unified memory architecture (uma), where the same memory array is used for cpu main memory and graphics frame-buffer. this means a reduction in total system memory for system performances that are equal to that of a comparable frame buffer and system memory based system, and generally much better, due to the higher memory bandwidth allowed by attaching the graphics engine directly to the 64-bit processor host interface running at the speed of the processor bus rather than the traditional pci bus. the 64-bit wide memory array provides the system with an 800mb/s peak bandwidth. this allows for higher resolution screens and greater color depth. the processor bus runs at 133 mhz, further increasing standard bandwidth by at least a factor of two. the standard pc chipset functions (dma, interrupt controller, timers, power management logic) are integrated together with the x86 processor core; additional low bandwidth functions such as communication ports are accessed by the stpc atlas via an internal isa bus. the pci bus is the main data communication link to the stpc atlas chip. the stpc atlas translates appropriate host bus i/o and memory cycles onto the pci bus. it also supports the generation of configuration cycles on the pci bus. the stpc atlas, as a pci bus agent (host bridge class), is compatible with pci specification 2.1. the chip- set also implements the pci mandatory header registers in type 0 pci configuration space for easy porting of pci aware system bios. the device contains a pci arbitration function for three external pci devices. figure 1-1 describes this architecture. 1.2. graphics features graphics functions are controlled through the on- chip svga controller and the monitor display is produced through the 2d graphics display engine. this graphics engine is tuned to work with the host cpu to provide a balanced graphics system with a low silicon area cost. it performs limited graphics drawing operations which include hardware acceleration of text, bitblts, transparent blts and fills. the results of these operations change the contents of the on-screen or off- screen frame buffer areas of sdram memory. the frame buffer can occupy a space up to 4 mbytes anywhere in the physical main memory. the maximum graphics resolution supported is 1280 x 1024 in 16 million colours at 75 hz refresh rate and is vga and svga compatible. horizontal timing fields are vga compatible while the vertical fields are extended by one bit to accommodate above display resolution. to generate the tft output, the stpc atlas extracts the digital video stream before the ramdac and reformats it to the tft format. the height and width of the flat panel are programmable. 1.3. interfaces an industry standard eide (ata 2) controller is built in to the stpc atlas and connected internally via the pci bus. the stpc atlas integrates two usb ports. universal serial bus (usb) is a general purpose communications interface for connecting peripherals to a pc. the usb open host controller interface (open hci) specification, revision 1.1, supports speeds of up to 12 mb/s. usb is royalty free and is likely to replace low- speed legacy serial, parallel, keyboard, mouse and floppy drive interfaces. usb revision 1.1 is fully supported under microsoft windows 98 and windows 2000. the stpc atlas pcmcia controller has been specifically designed to provide the interface with pcmcia cards which contain additional memory or i/o the power management control facilities include socket power control, insertion/removal capability, power saving with windows inactivity, ncs controlled chip power down, together with further controls for 3.3v suspend with modem ring resume detection.
general description 6/111 issue 1.0 - jul y 24, 2002 the stpc atlas implements a multi-function parallel port. the standard pc/at compatible logical address assignments for lpt1, lpt2 and lpt3 are supported. it can be configured for any of the following three modes and supports the ieee standard 1284 parallel interface protocol standards, as follows: - compatibility mode (forward channel, standard) - nibble mode (reverse channel, pc compatible) - byte mode (reverse channel, ps/2 compatible) the general purpose input/output (gpio) interface provides a 16-bit i/o facility, using 16 dedicated device pins. it is organised using two blocks of 8-bit registers, one for lines 0 to 7, the other for lines 8 to 15. each gpio port can be configured as an input or an output simply by programming the associated port direction control register. all gpio ports are configured as inputs at reset, which also latches the input levels into the strap registers. the input states of the ports are thus recorded automati- cally at reset, and this can be used as a strap register anywhere in the system. 1.4. feature multiplexing the stpc atlas bga package has 516 balls. this however is not sufficient for all of the integrated functions available; some features therefore share the same balls and cannot thus be used at the same time. the stpc atlas configuration is done by strap options. this is a set of pull-up or pull- down resistors on the memory data bus, checked on reset, which auto-configure the stpc atlas. there 3 multiplexed functions are the external isa bus, the local bus and the pcmcia interface. 1.5. power management the stpc atlas core is compliant with the advanced power management (apm) specification to provide a standard method by which the bios can control the power used by personal computers. the power management unit (pmu) module controls the power consumption, providing a comprehensive set of features that controls the power usage and supports compliance with the united states environmental protection agency's energy star computer program. the pmu provides the following hardware structures to assist the software in managing the system power consumption: - system activity detection. - 3 power-down timers detecting system inactivity: - doze timer (short durations). - stand-by timer (medium durations). - suspend timer (long durations). - house-keeping activity detection. - house-keeping timer to cope with short bursts of house-keeping activity while dozing or in stand-by state. - peripheral activity detection. - peripheral timer detecting peripheral inactivity - susp# modulation to adjust the system performance in various power down states of the system including full power-on state. - power control outputs to disable power from different planes of the board. lack of system activity for progressively longer periods of time is detected by the three power down timers. these timers can generate smi interrupts to cpu so that the smm software can put the system in decreasing states of power consumption. alternatively, system activity in a power down state can generate an smi interrupt to allow the software to bring the system back up to full power-on state. the chip-set supports up to three power down states described above; these correspond to decreasing levels of power savings. power down puts the stpc atlas into suspend mode. the processor completes execution of the current instruction, any pending decoded instructions and associated bus cycles. during the suspend mode, internal clocks are stopped. removing power-down, the processor resumes instruction fetching and begins execution in the instruction stream at the point it had stopped. because of the static nature of the core, no internal data is lost. 1.6. jtag jtag stands for joint test action group and is the popular name for ieee std. 1149.1, standard test access port and boundary-scan architec- ture. this built-in circuitry is used to assist in the test, maintenance and support of functional circuit blocks. the circuitry includes a standard interface through which instructions and test data are communicated. a set of test features is defined, including a boundary-scan register so that a component is able to respond to a minimum set of test instructions.
general description issue 1.0 - july 24, 2002 7/111 figure 1-1. functional description. x86 core host i/f sdram ctrl svga ge i/f vip pci m/s lb ctrl pci bus isa m/s ipc pci m/s isa bus crtc cursor monitor ide i/f pmu video pipeline c key k key lut local bus pcmcia i/os usb tft tft i/f video in jtag
general description 8/111 issue 1.0 - jul y 24, 2002 1.7. clock tree the stpc atlas integrates many features and generates all its clocks from a single 14mhz oscillator. this results in multiple clock domains as described in figure 1-2 . the speed of the plls is either fixed (devclk), either programmable by strap option (hclk) either programmable by software (dclk, mclk). when in synchronized mode, mclk speed is fixed to hclko speed and hclki is generated from mclki. figure 1-2. stpc atlas clock architecture kbd/mouse ipc sdram controller north bridge 14.31818 mhz xtalo xtali osc14m isaclk 1/4 devclk devclk (24mhz) pll (14mhz) 1/2 uarts hclk pll pciclki pciclko south bridge pwm 1/2 1/3 hclk dclk pll mclk pll dclk mclki mclko usb crtc,video,tft cpu x2 vclk 48mhz // port 1/4 1/2 1/26 1/6 vip ge, lde, afe pcmcia local bus host isa hclki hclko
general description issue 1.0 - july 24, 2002 9/111 figure 1-3. typical isa-based application. flash boot isa pci eide 2 serial ports parallel port svga tft irq dma.req dma.ack stpc atlas mouse keyboard usb vip rtc sdram 16 gpios romcs# 5v tolerant
general description 10/111 issue 1.0 - jul y 24, 2002 figure 1-4. typical pcmcia-based application. pci flash eide 2 serial ports parallel port svga tft stpc atlas mouse keyboard usb boot vip sdram 16 gpios romcs# pcmcia 5v tolerant
general description issue 1.0 - july 24, 2002 11/111 figure 1-5. typical local-bus-based application. flash boot pci stpc atlas rtc eide 2 serial ports parallel port svga tft mouse keyboard usb vip sdram 16 gpios irq local bus
general description 12/111 issue 1.0 - jul y 24, 2002
pin description issue 1.0 - july 24, 2002 13/111 2. pin description 2.1. introduction the stpc atlas integrates most of the functionalities of the pc architecture. therefore, many of the traditional interconnections between the host pc microprocessor and the peripheral devices are totally internal to the stpc atlas. this offers improved performance due to the tight coupling of the processor core and its peripherals. as a result many of the external pin connections are made directly to the on-chip peripheral functions. table 2-1 describes the physical implementation listing signal types and their functionalities. table 2-2 provides a full pin listing and description. table 2-6 provides a full listing of the stpc atlas package pin location physical connection. please refer to the pin allocation drawing for reference. due to the number of pins available for the package, and the number of functional i/os, some pins have several functions, selectable by strap option on reset. table 2-4 provides a summary of these pins and their functions. non multi-functional pins associated with a particular function are not available for use elsewhere when that function is disabled. for example, when in the isa mode, the local bus is disabled totally and local bus pins are set to the tri-state (high-impedance) condition. table 2-1. signal description group name qty basic clocks, reset & xtal (sys) 19 sdram controller (sdram) 95 pci controller 51 isa controller 80 100 local bus i/f 67 pcmcia controller 62 ide controller 34 vga controller (vga) / i 2 c10 video input port 11 tft output 24 usb controller 6 serial interface 16 keyboard/mouse controller 4 parallel port 18 gpio signals 16 jtag signals 5 miscellaneous 5 grounds 96 v dd 3.3 v/2.5 v 36 reserved 4 total pin count 516
pin description 14/111 issue 1.0 - jul y 24, 2002 table 2-2. definition of signal pins signal name dir buffer type 1 description qty basic clocks and resets sysrsti# i schmitt_ft system reset / power good 1 sysrsto# o bd8strp_ft reset output to system 1 xtali i osci13b 14.31818 mhz crystal input external oscillator input 1 xtalo o 14.31818 mhz crystal output 1 pci_clki i tlcht_ft 33 mhz pci input clock 1 pci_clko o bt8trp_tc 33 mhz pci output clock 1 isa_clk, isa_clk2x o bt8trp_tc isa clock x1 and x2 multiplexer select line for ipc 2 osc14m o bd8strp_ft isa bus synchronisation clock 1 hclk i/o bd4strp_ft 66 mhz host clock (test pin) 1 dev_clk o bt8trp_tc 24 mhz peripheral clock 1 dclk i/o bd4strp_ft 135 mhz dot clock 1 v dd _xxx_pll 2.5v power supply for pll clocks 7 memory controller mclki i tlcht_tc memory clock input 1 mclko o bt8trp_tc memory clock output 1 cs#[1:0] o bd8strp_tc dimm chip select 2 cs#[3]/ma[12]/ba[1] o bd16staruqp_tc dimm chip select memory address bank address 1 cs#[2]/ma[11] o bd16staruqp_tc dimm chip select memory address 1 ma[10:0] o bd16staruqp_tc memory row & column address 11 ba[0] o bd16staruqp_tc bank address 1 ras#[1:0] o bd16staruqp_tc row address strobe 2 cas#[1:0] o bd16staruqp_tc column address strobe 2 mwe# o bd16staruqp_tc write enable 1 md[0] i/o bd8strup_ft memory data 1 md[53:1] i/o bd8trp_tc memory data 53 md[63:54] i/o bd8strup_ft memory data 10 dqm[7:0] o bd8strp_tc data input/ouput mask 8 pci interface ad[31:0] i/o bd8pciarp_ft address / data 32 cbe[3:0] i/o bd8pciarp_ft bus commands / byte enables 4 frame# i/o bd8pciarp_ft cycle frame 1 trdy# i/o bd8pciarp_ft target ready 1 irdy# i/o bd8pciarp_ft initiator ready 1 stop# i/o bd8pciarp_ft stop transaction 1 devsel# i/o bd8pciarp_ft device select 1 par i/o bd8pciarp_ft parity signal transactions 1 perr# i/o bd8pciarp_ft parity error 1 serr# o bd8pciarp_ft system error 1 lock# i tlcht_ft pci lock 1 pci_req#[2:0] i bd8pciarp_ft pci request 3 pci_gnt#[2:0] o bd8pciarp_ft pci grant 3 pci_int#[3:0] i bd4strup_ft pci interrupt request 4 note 1 ; see table 2-3 for buffer type descriptions
pin description issue 1.0 - july 24, 2002 15/111 isa bus interface la[23:17] o bd8strup_ft unlatched address bus 7 sa[19:0] o bd8strup_ft latched address bus 20 sd[15:0] i/o bd8strp_ft data bus 16 iochrdy i bd8strup_ft i/o channel ready 1 ale o bd4strp_ft address latch enable 1 bhe# o bd8strup_ft system bus high enable 1 memr#, memw# i/o bd8strup_ft memory read & write 2 smemr#, smemw# o bd8strp_ft system memory read and write 2 ior#, iow# i/o bd8strup_ft i/o read and write 2 master# i bd4strup_ft add on card owns bus 1 mcs16# i bd4strup_ft memory chip select 16 1 iocs16# i bd4strup_ft i/o chip select 16 1 ref# i bd8strp_ft refresh cycle 1 aen o bd8strup_ft address enable 1 iochck# i bd4strup_ft i/o channel check (isa) 1 rtcrw# o bd4strp_ft rtc read / write# 1 rtcds# o bd4strp_ft rtc data strobe 1 rtcas o bd4strp_ft rtc address strobe 1 rmrtccs# o bd4strp_ft rom / rtc chip select 1 gpiocs# i/o bd4strp_ft general purpose chip select 1 irq_mux[3:0] i bd4strp_ft multiplexed interrupt request 4 dack_enc[2:0] o bd4strp_ft dma acknowledge 3 dreq_mux[1:0] i bd4strp_ft multiplexed dma request 2 tc o bd4strp_ft isa terminal count 1 isaoe# i bd4strp_ft isa (0) / ide (1) selection 1 kbcs# i/o bd4strp_ft external keyboard chip select 1 zws# i bd4strp_ft zero wait state 1 pcmcia interface reset o bd8strp_ft reset 1 a[23:0] o bd8strup_ft address bus 24 d[15:0] i/o bd8strp_ft data bus 16 iord#, iowr# o bd8strup_ft i/o read and write 2 wp / iois16# i bd4strup_ft dma request // write protect i/o size is 16 bit 1 bvd2, bvd1 i bd4strup_ft battery voltage detect 2 ready# / ireq# i bd4strup_ft busy / ready# // interrupt request 1 wait# i bd8strup_ft wait 1 oe# o bd8strup_ft output enable // dma terminal count 1 we# o bd4strp_ft write enable // dma terminal count 1 reg# o bd4strup_ft dma acknowledge // register 1 cd2#, cd1# i bd4strup_ft card detect 2 ce2#, ce1# o bd4strp_ft card enable 2 vcc5_en o bd4strp_ft power switch control: 5 v power 1 vcc3_en o bd8strp_ft power switch control: 3.3 v power 1 vpp_pgm o bd8strp_ft power switch control: program power 1 vpp_vcc o bd4strp_ft power switch control: vcc power 1 gpi# i bd4strp_ft general purpose input 1 table 2-2. definition of signal pins signal name dir buffer type 1 description qty note 1 ; see table 2-3 for buffer type descriptions
pin description 16/111 issue 1.0 - jul y 24, 2002 local bus interface pa[24:20,15,9:8,3:0] o bd4strp_ft address bus [24:20], [15], [9:8], [3:0] 12 pa[19,11] o bd8strp_ft address bus [19], [11] 2 pa[18:16,14:12,7:4] o bd8strup_ft address bus [18:16], [14:12], [7:4] 10 pa[10] o bd4strup_ft address bus [10] 1 pd[15:0] i/o bd8strp_ft data bus [15:0] 16 prd# o bd4strup_ft memory and i/o read signal 1 pwr# o bd4strup_ft memory and i/o write signal 1 prdy i bd8strup_ft data ready 1 iocs#[7:4] o bd4strup_ft i/o chip select 4 iocs#[3] o bd4strp_ft i/o chip select 1 iocs#[2:0] o bd8strup_ft i/o chip select 3 pbe#[1] o bd8strp_ft upper byte enable (pd[15:8]) 1 pbe#[0] o bd4strup_ft lower byte enable (pd[7:0]) 1 fcs0# o bd4strp_ft flash bank 0 chip select 1 fcs1# o bt8trp_tc flash bank 1 chip select 1 fcs_0h# o bd8strp_ft upper half bank 0 flash chip select 1 fcs_0l# o bd8strp_ft lower half bank 0 flash chip select 1 fcs_1h# o bd8strp_ft upper half bank 1 flash chip select 1 fcs_1l# o bd8strp_ft lower half bank 1 flash chip select 1 irq_mux[3:0] 1 i/o bd4strp_ft muxed interrupt lines 4 ide controller dd[15:12] i/o bd4strp_ft data bus 4 dd[11:0] i/o bd8strup_ft data bus 12 da[2:0] o bd8strup_ft address bus 3 pcs1, pcs3 o bd8strup_ft primary chip selects 2 scs1, scs3 o bd8strup_ft secondary chip selects 2 diordy o bd8strup_ft data i/o ready 1 pirq/sirq i bd4strp_ft primary / secondary interrupt request 2 pdrq/sdrq i bd4strp_ft primary / secondary dma request 2 pdack#/sdack# o bd8strp_ft primary / secondary dma acknowledge 2 pdior#/sdior# o bd8strup_ft primary / secondary io read 2 pdiow#/sdiow# o bd8strp_ft primary / secondary io write 2 vga controller red, green, blue o vddco red, green, blue 3 vsync, hsync i/o bd4strp_ft vertical & horizontal synchronisations 2 vref_dac i ana dac voltage reference 1 rset i ana resistor set 1 comp i ana compensation 1 col_sel o bd4strp_ft colour select 1 i2c interface scl / ddc[1] i/o bd4strup_ft i2c interface - clock / vga ddc[1] 1 sda / ddc[0] i/o bd4strup_ft i2c interface - data / vga ddc[0] 1 tft interface tftr[5:2] o bd4strp_tc red 4 tftr[1:0] o bd4strp_ft red 2 tftg[5:2] o bd4strp_tc green 4 ,tftg[1:0] o bd4strp_ft green 2 table 2-2. definition of signal pins signal name dir buffer type 1 description qty note 1 ; see table 2-3 for buffer type descriptions
pin description issue 1.0 - july 24, 2002 17/111 tftb[5:2] o bd4strp_tc blue 4 tftb[1:0] o bd4strp_ft blue 2 tftline o bd8strp_tc horizontal sync 1 tftframe o bd4strp_tc vertical sync 1 tftde o bd4strp_tc data enable 1 tftenvdd, tftenvcc o bd4strp_tc enable vdd & vcc of flat panel 2 tftpwm o bd8strp_tc pwm back-light control 1 tftdclk o bt8trp_tc dot clock for flat panel 1 video input port vclk i/o bd8strp_ft 27-33 mhz video input port clock 1 vin[7:0] i bd4strp_ft video input data bus 8 odd_even# i/o bd4strp_ft video input odd/even field 1 vcs i/o bd4strp_ft video input horizontal sync 1 usb interface oc i tlchtu_tc over current detect 1 usbdpls[0] 1 usbdmns[0] 1 i/o usbds_2v5 universal serial bus port 0 2 usbdpls[1] 1 usbdmns[1] 1 i/o usbds_2v5 universal serial bus port 1 2 poweron 1 o bt4crp usb power supply lines 1 serial controller cts0#, cts1# i tlcht_ft clear to send, msr[4] status bit 2 dcd0#, dcd1# i tlcht_ft data carrier detect, msr[7] status bit 2 dsr0#, dsr1# i tlcht_ft data set ready, msr[5] status bit. 2 dtr0#, dtr1# o bd4strp_tc data terminal ready, msr[0] status bit 2 ri0#, ri1# i tlcht_ft ring indicator, msr[6] status bit 2 rts0#, rts1# o bd4strp_tc request to send, msr[1] status bit 2 rxd0, rxd1 i tlcht_ft receive data, input serial input 2 txd0, txd1 o bd4strp_tc transmit data, serial output 2 keyboard & mouse interface kbclk i/o bd4strp_tc keyboard clock line 1 kbdata i/o bd4strp_tc keyboard data line 1 mclk i/o bd4strp_tc mouse clock line 1 mdata i/o bd4strp_tc mouse data line 1 parallel port pe i bd14starp_ft paper end 1 slct i bd14starp_ft select 1 busy# i bd14starp_ft busy 1 err# i bd14starp_ft error 1 ack# i bd14starp_ft acknowledge 1 pdir# o bd14starp_ft parallel device direction 1 strobe# o bd14starp_ft pcs / strobe# 1 init# o bd14starp_ft init 1 autofd# o bd14starp_ft automatic line feed 1 slctin# o bd14starp_ft select in 1 ppd[7:0] i/o bd14starp_ft data bus 8 table 2-2. definition of signal pins signal name dir buffer type 1 description qty note 1 ; see table 2-3 for buffer type descriptions
pin description 18/111 issue 1.0 - jul y 24, 2002 gpio signals gpio[15:0] i/o bd4strp_ft general purpose ios 16 jtag tclk i tlcht_ft test clock 1 trst i tlcht_ft test reset 1 tdi i tlchtd_ft test data input tms i tlcht_ft test mode set 1 tdo o bt8trp_tc test data output 1 miscellaneous scan_enable i tlchtd_ft test pin - reserved 1 spkrd o bd4strp_ft speaker device output 1 table 2-2. definition of signal pins signal name dir buffer type 1 description qty note 1 ; see table 2-3 for buffer type descriptions table 2-3. buffer type descriptions buffer description ana analog pad buffer osci13b oscillator, 13 mhz, hcmos bt4crp lvttl output, 4 ma drive capability, tri-state control bt8trp_tc lvttl output, 8 ma drive capability, tri-state control, schmitt trigger bd4strp_ft lvttl bi-directional, 4 ma drive capability, schmitt trigger, 5v tolerant bd4strup_ft lvttl bi-directional, 4 ma drive capability, schmitt trigger, pull-up, 5v tolerant bd4strp_tc lvttl bi-directional, 4 ma drive capability, schmitt trigger bd8strp_ft lvttl bi-directional, 8 ma drive capability, schmitt trigger, 5v tolerant bd8strup_ft lvttl bi-directional, 8 ma drive capability, schmitt trigger, pull-up, 5v tolerant bd8strp_tc lvttl bi-directional, 8 ma drive capability, schmitt trigger bd8trp_tc lvttl bi-directional, 8 ma drive capability, schmitt trigger bd8pciarp_ft lvttl bi-directional, 8 ma drive capability, pci compatible, 5v tolerant bd14starp_ft lvttl bi-directional, 14 ma drive capability, schmitt trigger, ieee1284 compliant, 5v tolerant bd16staruqp_tc lvttl bi-directional, 16 ma drive capability, schmitt trigger schmitt_ft lvttl input, schmitt trigger, 5v tolerant tlcht_ft lvttl input, 5v tolerant tlcht_tc lvttl input tlchtd_tc lvttl input, pull-down tlchtu_tc lvttl input, pull-up usbds_2v5 usb 1.1 compliant pad buffer vddco analog output pad
pin description issue 1.0 - july 24, 2002 19/111 2.2. signal descriptions 2.2.1. basic clocks and resets sysrsti# system reset/power good. this input is low when the reset switch is depressed. otherwise, it reflects the power supplys power good signal. pwgd is asynchronous to all clocks, and acts as a negative active reset. the reset circuit initiates a hard reset on the rising edge of pwgd. note that while reset is being asserted, the signals on the device pins are in an unknown state. sysrsto# reset output to system. this is the system reset signal and is used to reset the rest of the components (not on host bus) in the system. the isa bus reset is an externally inverted buffered version of this output and the pci bus reset is an externally buffered version of this output. xtali 14.3 mhz crystal input xtalo 14.3 mhz crystal output. these pins are provided for the connection of an external 14.318 mhz crystal to provide the reference clock for the internal frequency synthesizer, from which the hclk and clk24m signals are generated. pci_clki 33 mhz pci input clock. this signal must be connected to a clock generator and is usually connected to pci_clko. pci_clko 33 mhz pci output clock. this is the master pci bus clock output. isa_clk isa clock output (also multiplexer select line for ipc). this pin produces the clock signal for the isa bus. it is also used with isa_clk2x as the multiplexer control lines for the interrupt controller interrupt input lines. this is a divided down version of the pciclk or osc14m. isa_clkx2 isa clock output (also multiplexer select line for ipc). this pin produces a signal at twice the frequency of the isa bus clock signal. it is also used with isa_clk as the multiplexer control lines for the interrupt controller interrupt input lines. clk14m isa bus synchronisation clock. this is the buffered 14.318 mhz clock to the isa bus. hclk host clock. this is the host clock. its frequency can vary from 25 to 66 mhz. all host transactions and pci transactions are synchronized to this clock. host transactions executed by the dram controller are also driven by this clock. dev_clk 24 mhz peripheral clock (floppy drive). this 24 mhz signal is provided as a convenience for the system integration of a floppy disk driver function in an external chip. this clock signal is not available in local bus mode. dclk 135 mhz dot clock. this is the dot clock, which drives graphics display cycles. its frequency can be as high as 135 mhz, and it is required to have a worst case duty cycle of 60-40. for further details, refer to section 3.1.4. bit 4. 2.2.2. memory interface mclki memory clock input. this clock is driving the sdram controller, the graphics engine and display controller. this input should be a buffered version of the mclko signal with the track lengths between the buffer and the pin matched with the track lengths between the buffer and the memory banks. mclko memory clock output. this clock drives the memory banks on board and is generated from an internal pll. the stpc atlas mclock signal can run up to 100mhz reliably, but pcb layout is so critical that the maximum guaranteed speed is 90mhz cs#[1:0] chip select these signals are used to disable or enable device operation by masking or enabling all sdram inputs except mclk, cke, and dqm. cs#[2]/ma[11] chip select/bank address this pin is cs#[2] in the case when 16-mbit devices are used. for all other densities, it becomes ma[11]. cs#[3]/ma[12]/ba[1] chip select/ memory address/ bank address this pin is cs#[3] in the case when 16 mbit devices are used. for all other densities, it becomes ma[12] when 2 internal banks devices are used and ba[1] when 4 internal bank devices are used. ma[10:0] memory address. multiplexed row and column address lines. ba[0] bank address. internal bank address line. md[63:0] memory data. this is the 64-bit memory data bus. this bus is also used as input at the rising edge of sysrsti# to latch in power-up configuration information into the adpc strap registers. ras#[1:0] row address strobe. there are two active-low row address strobe output signals. the ras# signals drive the memory devices directly without any external buffering.
pin description 20/111 issue 1.0 - jul y 24, 2002 cas#[1:0] column address strobe. there are two active-low column address strobe output signals. the cas# signals drive the memory devices directly without any external buffering. mwe# write enable. write enable specifies whether the memory access is a read (mwe# = h) or a write (mwe# = l). this single write enable controls all drams. the mwe# signals drive the memory devices directly without any external buffering. 2.2.3. pci interface ad[31:0] pci address/data. this is the 32-bit multiplexed address and data bus of the pci. this bus is driven by the master during the address phase and data phase of write transactions. it is driven by the target during data phase of read transactions. pbe[3:0]# bus commands/byte enables. these are the multiplexed command and byte enable signals of the pci bus. during the address phase they define the command and during the data phase they carry the byte enable information. these pins are inputs when a pci master other than the stpc atlas owns the bus and outputs when the stpc atlas owns the bus. frame# cycle frame. this is the frame signal of the pci bus. it is an input when a pci master owns the bus and is an output when stpc atlas owns the pci bus. trdy# target ready. this is the target ready signal of the pci bus. it is driven as an output when the stpc atlas is the target of the current bus transaction. it is used as an input when stpc atlas initiates a cycle on the pci bus. irdy# initiator ready. this is the initiator ready signal of the pci bus. it is used as an output when the stpc atlas initiates a bus cycle on the pci bus. it is used as an input during the pci cycles targeted to the stpc atlas to determine when the current pci master is ready to complete the current transaction. stop# stop transaction. stop# is used to implement the disconnect, retry and abort protocol of the pci bus. it is used as an input for the bus cycles initiated by the stpc atlas and is used as an output when a pci master cycle is targeted to the stpc atlas. devsel# device select. this signal is used as an input when the stpc atlas initiates a bus cycle on the pci bus to determine if a pci slave device has decoded itself to be the target of the current transaction. it is asserted as an output either when the stpc atlas is the target of the current pci transaction or when no other device asserts devsel# prior to the subtractive decode phase of the current pci transaction. par parity signal transactions. this is the parity signal of the pci bus. this signal is used to guarantee even parity across ad[31:0], cbe[3:0]#, and par. this signal is driven by the master during the address phase and data phase of write transactions. it is driven by the target during data phase of read transactions. (its assertion is identical to that of the ad bus delayed by one pci clock cycle) perr# parity error serr# system error. this is the system error signal of the pci bus. it may, if enabled, be asserted for one pci clock cycle if target aborts a stpc atlas initiated pci transaction. its assertion by either the stpc atlas or by another pci bus agent will trigger the assertion of nmi to the host cpu. this is an open drain output. lock# pci lock. this is the lock signal of the pci bus and is used to implement the exclusive bus operations when acting as a pci target agent. pci_req#[2:0] pci request. these pins are the three external pci master request pins. they indicates to the pci arbiter that the external agents desire use of the bus. pci_gnt#[2:0] pci grant. these pins indicate that the pci bus has been granted to the master requesting it on its pci_req#. pci_int#[3:0] pci interrupt request. these are the pci bus interrupt signals. they are to be encoded before connection to the stpc atlas using isaclk and isaclkx2 as the input selection strobes. 2.2.4. isa bus interface la[23:17] unlatched address. these unlatched isa bus pins address bits 23-17 on 16-bit devices. when the isa bus is accessed by any cycle initiated from the pci bus, these pins are in output mode. when an isa bus master owns the bus, these pins are tristated. sa[19:0] unlatched address. these are the 20 low bits of the system address bus of isa. these pins are used as an input when an isa bus master owns the bus and are outputs at all other times. sd[15:0] i/o data bus (isa). these are the external isa databus pins. iochrdy io channel ready. iochrdy is the io channel ready signal of the isa bus and is driven as an output in response to an isa master cycle targeted to the host bus or an internal register of
pin description issue 1.0 - july 24, 2002 21/111 the stpc atlas. the stpc atlas monitors this signal as an input when performing an isa cycle on behalf of the host cpu, dma master or refresh. isa masters which do not monitor iochrdy are not guaranteed to work with the stpc atlas since the access to the system memory can be considerably delayed due to crt refresh or a write back cycle. ale address latch enable. this is the address latch enable output of the isa bus and is asserted by the stpc atlas to indicate that la23-17, sa19- 0, aen and sbhe# signals are valid. the ale is driven high during refresh, dma master or an isa master cycles by the stpc atlas. ale is driven low after reset. bhe# system bus high enable. this signal, when asserted, indicates that a data byte is being transferred on sd15-8 lines. it is used as an input when an isa master owns the bus and is an output at all other times. memr# memory read. this is the memory read command signal of the isa bus. it is used as an input when an isa master owns the bus and is an output at all other times. the memr# signal is active during refresh. memw# memory write. this is the memory write command signal of the isa bus. it is used as an input when an isa master owns the bus and is an output at all other times. smemr# system memory read. the stpc atlas generates smemr# signal of the isa bus only when the address is below one mbyte or the cycle is a refresh cycle. smemw# system memory write. the stpc atlas generates smemw# signal of the isa bus only when the address is below one mbyte. ior# i/o read. this is the io read command signal of the isa bus. it is an input when an isa master owns the bus and is an output at all other times. iow# i/o write. this is the io write command signal of the isa bus. it is an input when an isa master owns the bus and is an output at all other times. master# add on card owns bus. this signal is active when an isa device has been granted bus ownership. mcs16# memory chip select16. this is the decode of la23-17 address pins of the isa address bus without any qualification of the command signal lines. mcs16# is always an input. the stpc atlas ignores this signal during io and refresh cycles. iocs16# io chip select16. this signal is the decode of sa15-0 address pins of the isa address bus without any qualification of the command signals. the stpc atlas does not drive iocs16# (similar to pc-at design). an isa master access to an internal register of the stpc atlas is executed as an extended 8-bit io cycle. ref# refresh cycle. this is the refresh command signal of the isa bus. it is driven as an output when the stpc atlas performs a refresh cycle on the isa bus. it is used as an input when an isa master owns the bus and is used to trigger a refresh cycle. the stpc atlas performs a pseudo hidden refresh. it requests the host bus for two host clocks to drive the refresh address and capture it in external buffers. the host bus is then relinquished while the refresh cycle continues on the isa bus. aen address enable. address enable is enabled when the dma controller is the bus owner to indicate that a dma transfer will occur. the enabling of the signal indicates to io devices to ignore the ior#/iow# signal during dma transfers. iochck# io channel check. io channel check is enabled by any isa device to signal an error condition that can not be corrected. nmi signal becomes active upon seeing iochck# active if the corresponding bit in port b is enabled. gpiocs# i/o general purpose chip select 1. this output signal is used by the external latch on isa bus to latch the data on the sd[7:0] bus. the latch can be use by pmu unit to control the external peripheral devices to power down or any other desired function. rtcrw# real time clock rw#. this pin is used as rtcrw#. this signal is asserted for any i/o write to port 71h. rtcds# real time clock ds . this pin is used as rtcds#. this signal is asserted for any i/o read to port 71h. its polarity complies with the ds pin of the mt48t86 rtc device when configured with intel timings. rtcas real time clock address strobe. this signal is asserted for any i/o write to port 70h. rmrtccs# rom/real time clock chip select. this pin is a multi-function pin. this signal is asserted if a rom access is decoded during a memory cycle. it should be combined with memr# or memw# signals to properly access the rom. during an io cycle, this signal is asserted if access to the real time clock (rtc) is decoded. it should be combined with ior# or iow# signals to properly access the real time clock.
pin description 22/111 issue 1.0 - jul y 24, 2002 irq_mux[3:0] multiplexed interrupt request. these are the isa bus interrupt signals. they are to be encoded before connection to the stpc atlas using isaclk and isaclkx2 as the input selection strobes. note that irq8b, which by convention is connected to the rtc, is inverted before being sent to the interrupt controller, so that it may be connected directly to the irq# pin of the rtc. isaoe# bidirectional oe control. this signal controls the oe signal of the external transceiver that connects the ide dd bus and isa sa bus. kbcs# keyboard chip select. this signal is asserted if a keyboard access is decoded during a i/o cycle. zws# zero wait state. this signal, when asserted by addressed device, indicates that current cycle can be shortened. dack_enc[2:0] dma acknowledge. these are the isa bus dma acknowledge signals. they are encoded by the stpc atlas before output and should be decoded externally using isaclk and isaclkx2 as the control strobes. dreq_mux[1:0] isa bus multiplexed dma request. these are the isa bus dma request signals. they are to be encoded before connection to the stpc atlas using isaclk and isaclkx2 as the input selection strobes. tc isa terminal count. this is the terminal count output of the dma controller and is connected to the tc line of the isa bus. it is asserted during the last dma transfer, when the byte count expires. 2.2.5. pcmcia interface reset card reset. this output forces a hard reset to a pc card. a[25:0] address bus. these are the 25 low bits of the system address bus of the pcmcia bus. these pins are used as an input when an pcmcia bus owns the bus and are outputs at all other times. d[15:0] i/o data bus (pcmcia). these are the external pcmcia databus pins. iord# i/o read. this output is used with reg# to gate i/o read data from the pc card, (only when reg# is asserted). iowr# i/o write . this output is used with reg# to gate i/o write data from the pc card, (only when reg# is asserted). wp write protect. this input indicates the status of the write protect switch (if fitted) on memory pc cards (asserted when the switch is set to write protect). bvd1, bvd2 battery voltage detect. these inputs will be generated by memory pc cards that include batteries and are an indication of the condition of the batteries. bvd1 and bvd2 are kept asserted high when the battery is in good condition. ready#/busy#/ireq# ready/busy/interrupt request. this input is driven low by memory pc cards to signal that their circuits are busy processing a previous write command. wait# bus cycle wait. this input is driven by the pc card to delay completion of the memory or i/o cycle in progress. oe# output enable. oe# is an active low output which is driven to the pc card to gate memory read data from memory pc cards. we#/prgm# write enable. this output is used by the host for gating memory write data. we# is also used for memory pc cards that have programmable memory. reg# attribute memory select. this output is inactive (high) for all normal accesses to the main memory of the pc card. i/o pc cards will only respond to iord# or iowr# when reg# is active (low). also see section 2.2.7. cd1#, cd2# card detect. these inputs provide for the detection of correct card insertion. cd#1 and cd#2 are positioned at opposite ends of the connector to assist in the detection process. these inputs are internally grounded on the pc card therefore they will be forced low whenever a card is inserted in a socket. ce1#, ce2# card enable . these are active low output signals provided from the pcic. ce#1 enables even bytes, ce#2 odd bytes. enable# enable. this output is used to activate/ select a pc card socket. enable# controls the external address buffer logic.c card has been detected (cd#1 and cd#2 = '0'). enif# enif . this output is used to activate/select a pc card socket. ext_dir external transceiver direction control. this output is high during a read and low during a write. the default power up condition is write (low). used for both low and high bytes of the data bus. vcc_en#, vpp1_en0, vpp1_en1, vpp 2_en0, vpp2_en1 power control. five output signals
pin description issue 1.0 - july 24, 2002 23/111 used to control voltages (vpp1, vpp2 and vcc) to a pc card socket. also see section 13.7.5. gpi# general purpose input. this signal is hardwired to 1. 2.2.6. local bus pa[24:0] address bus output. pd[15:0] data bus. this is the 16-bit data bus. d[7:0] is the lsb and pd[15:8] is the msb. prd#[1:0] read control output . these are memory and i/o read signals. prd0# is used to read the lsb and prd1# to read the msb. pwr#[1:0] write control output. these are memory and i/o write signals. pwr0# is used to write the lsb and pwr1# to write the msb. prdy data ready input. this signal is used to create wait states on the bus. when high, it completes the current cycle. fcs#[1:0] two flash memory chip select outputs. these are the programmable chip select signals for flash memory. iocs#[7:0] i/o chip select output. these are the programmable chip select signals for up to 4 external i/o devices. pbe#[1:0] byte enable. these are the byte enables that identifies on which databus the date is valid. pbe#[0] corres ponds to pd[7:0] and pbe#[1] corresponds to pd[15:8]. these are normally used when 8 bit transfers are transfered across the 16 bit bus. irq_mux#[3:0] multiplexed interrupt lines. 2.2.7. ipc dack_enc[2:0] dma acknowledge. these are the isa bus dma acknowledge signals. they are encoded by the stpc industrial before output and should be decoded externally using isaclk and isaclkx2 as the control strobes. dreq_mux[1:0] isa bus multiplexed dma request. these are the isa bus dma request signals. they are to be encoded before connection to the stpc industrial using isaclk and isaclkx2 as the input selection strobes. tc isa terminal count. this is the terminal count output of the dma controller and is connected to the tc line of the isa bus. it is asserted during the last dma transfer, when the byte count expires. 2.2.8. ide interface da[2:0] address. these signals are connected to da[2:0] of ide devices directly or through a buffer. if the toggling of signals are to be masked during isa bus cycles, they can be externally ored with isaoe# before being connected to the ide devices. dd[15:0] databus. when the ide bus is active, they serve as ide signals dd[11:0]. ide devices are connected to sa[19:8] directly and isa bus is connected to these pins through two ls245 transceivers. pcs1, pcs3, scs1, scs3 primary & secondary chip selects. these signals are used as the active high primary and secondary master & slave ide chip select signals. these signals must be externally nanded with the isaoe # signal before driving the ide devices to guarantee it is active only when isa bus is idle. in local bus mode, they just need to be inverted. diordy busy/ready. this pin serves as ide signal diordy. pirq primary interrupt request. sirq secondary interrupt request. interrupt request from ide channels. pdrq primary dma request. sdrq secondary dma request. dma request from ide channels. pdack# primary dma acknowledge. sdack# secondary dma acknowledge. dma acknowledge to ide channels. pdior#, pdiow# primary i/o read & write. sdior#, sdiow# secondary i/o read & write . primary & secondary channel read & write. 2.2.9. monitor interface red, green, blue rgb video outputs. these are the 3 analog colour outputs from the ramdacs. these signals are sensitive to interference, therefore they need to be properly shielded. vsync vertical synchronisation pulse. this is the vertical synchronization signal from the vga controller. hsync horizontal synchronisation pulse. this is the horizontal synchronization signal from the vga controller. vref_dac dac voltage reference. this pin is an input driving the digital to analog converters. this allows an external voltage reference source to be used.
pin description 24/111 issue 1.0 - jul y 24, 2002 rset resistor current set. this is the reference current input to the ramdac. used to set the full- scale output of the ramdac. comp compensation. this is the ramdac compensation pin. normally, an external capacitor (typically 10nf) is connected between this pin and v dd to damp oscillations. ddc[1:0] direct data channel serial link. these bidirectional pins are connected to crtc register 3fh to implement ddc capabilities. they conform to i 2 c electrical specifications, they have open- collector output drivers which are internally connected to v dd through pull-up resistors. they can instead be used for accessing i2c devices on board. ddc1 and ddc0 correspond to scl and sda respectively. 2.2.10. video interface vclk pixel clock input. this signal is used to synchronise data being transferred from an external video device to either the frame buffer, or alternatively out the tv output in bypass mode. this pin can be sourced from stpc if no external vclk is detected, or can be input from an external video clock source. vin[7:0] yuv video data input itu-r 601 or 656. time multiplexed 4:2:2 luminance and chrominance data as defined in itu-r rec601-2 and rec656 (except for ttl input levels). this bus typically carries a stream of cb,y,cr,y digital video at vclk frequency, clocked on the rising edge (by default) of vclk. vcs line synchronisation input. this is the horizontal synchronisation of the incomming ccir601 video. the signal is synchronous to rising edge of vclk. odd_even frame synchronisation output. this is the vertical synchronisation of the incomming ccir601 video. the signal is synchronous to rising edge of vclk. the default polarity for this pin is: - odd (not-top) field: low level - even (bottom) field: high level 2.2.11. tft interface signals the tft (thin film transistor) interface converts signals from the crt controller into control signals for an external tft flat panel. the signals are listed below. tftframe, vertical sync. pulse output. tftline, horizontal sync. pulse output. tftde, data enable. tftr5-0, red output. tftg5-0, green output. tftb5-0, blue output . tftenvdd, enable vdd of flat panel. tftenvcc, enable vcc of flat panel. pwm pwm back-light control. this pwm is clocked by the pci clock. tftdclk, dot clock for the flat panel. 2.2.12. usb interface oc over current detect this signal is used to monitor the status of the usb power supply lines of both devices. usb port are disabled when oc signal is asserted. usbdpl0, usbdmns0 universal serial bus data 0 this signal pair comprises the differential data signal for usb port 0. usbdpl1, usbdmns1 universal serial bus port 1 this signal pair comprises the differential data signal for usb port 1. poweron usb power supply lines 2.2.13. serial interface rxd0, rxd1 serial input. data is clocked in using rclk/16. txd0, txd1 serial output. data is clocked out using tclk/16 (tclk=baud#). dcd0#, dcd1# input data carrier detect. ri0#, ri1# input ring indicator. dsr0#, dsr1# input data set ready. cts0#, cts1# input clear to send. rts0#, rts1# output request to send. dtr0#, dtr1# output data terminal read. 2.2.14. keyboard/mouse interface kbclk, keyboard clock line. keyboard data is latched by the controller on each negative clock edge produced on this pin. the keyboard can be disabled by pulling this pin low by software control. kbdata, keyboard data line. 11-bits of data are shifted serially through this line when data is being transferred. data is synchronised to kbclk.
pin description issue 1.0 - july 24, 2002 25/111 mclk, mouse clock line. mouse data is latched by the controller on each negative clock edge produced on this pin. the mouse can be disabled by pulling this pin low by software control. mdata, mouse data line. 11-bits of data are shifted serially through this line when data is being transferred. data is synchronised to mclk. 2.2.15. parallel port pe paper end. input status signal from printer. slct printer select. printer selected input. busy# printer busy . input status signal from printer. err# error . input status signal from printer. ack# acknowledge. input status signal from printer. pddir# parallel device direction. bidirectional control line output. strobe# pcs/strobe#. data transfer strobe line to printer. init# initialize printer. this output sends an initialize command to the connected printer. autofd# automatic line feed. this output sends a command to the connected printer to automatically generate line feed on received carriage returns. slctin# select in. printer select output. ppd[7-0] parallel port data lines data transfer lines to printer. bidirectional depending on modes. 2.2.16. miscellaneous spkrd speaker drive. this is the output to the speaker and is the and of the counter 2 output with bit 1 of port 61h and drives an external speaker driver. this output should be connected to a 7407 type high voltage driver. scan_enable reserved . this pin is reserved for test and miscellaneous functions. it has to be set to 0 or connected to ground in normal operation. col_sel colour select. can be used for picture in picture function. note however that this signal, brought out from the video pipeline, is not in sync with the vga output signals, i.e. the vga signals run four clock cycles after the col_sel signal. 2.2.17. jtag interface tclk test clock tdi test data input tms test mode input tdo test data output trst test reset input
pin description 26/111 issue 1.0 - jul y 24, 2002 2.3. signal detail the muxing between isa, local bus and pcmcia is performed by external strap options. the resulting interface is then dynamically muxed with the ide interface. table 2-4. multiplexed signals (on the same pin) ide pin name isa pin name pcmcia pin names local bus pin name diordy iochrdy - da[2] la[19] = 0 da[1:0] la[18:17] a[25:24] scs3,scs1 la[23:22] a[23:22] pcs3,pcs1 la[21:20] a[21:20] dd[15] rmrtccs# romcs# dd[14] kbcs# hi-z dd[13:12] rtcrw#, rtcds# hi-z dd[11:0] sa[19:8] a[19:8] sd[15:0] d[15:0] pd[15:0] rtcas = 0 fcs0# dev_clk dev_clk fcs1# sa[3] a[3] prdy sa[2:0] a[2:0] iocs#[2:0] smemw# vpp_pgm pbe#[1] iocs16# wp/iois16# pbe#[0] master# bvd1 prd# mcs16# = 0 pwr# dack_enc [2:0] = 0x04 pa[2:0] tc = 0 pa[3] sa[7:4] a[7:4] pa[7:4] zws# gpi# pa[8] gpiocs# vcc5_en pa[9] iochck# bvd2 pa[10] ref# reset pa[11] iow# iowr# pa[12] ior# iord# pa[13] memr# = 0 pa[14] ale = 0 pa[15] aen wait# pa[16] bhe# oe# pa[17] memw# = 0 pa[18] smemr# vcc3_en pa[19] dreq_mux#[1:0] ce2#, ce1# pa[21:20] hi-z hi-z pa[22] hi-z vpp_vcc pa[23] hi-z we# pa[24] hi-z reg# iocs#[7] hi-z ready# iocs#[6] hi-z cd1#, cd2# iocs#[5], iocs#[4] isaoe# = 1 isaoe# = 0 isaoe# = 0 iocs#[3]
pin description issue 1.0 - july 24, 2002 27/111 table 2-5. signal value on reset signal name sysrsti# active sysrsti# inactive sysrsto# active release of sysrsto# basic clocks and resets xtalo 14mhz isa_clk low 7mhz isa_clk2x 14mhz osc14m 14mhz dev_clk 24mhz hclk oscillating at the speed defined by the strap options. pci_clko hclk divided by 2 or 3, depending on the strap options. dclk 17mhz memory controller mclko 66mhz if asynchonous mode, hclk speed if synchronized mode. cs#[3:1] high cs#[0] high sdram init sequence: write cycles ma[10:0], ba[0] 0x00 ras#[1:0], cas#[1:0] high mwe#, dqm[7:0] high md[63:0] input pci interface ad[31:0] 0x0000 first prefetch cycles when not in local bus mode. cbe[3:0], par low frame#, trdy#, irdy# input stop#, devsel# input perr#, serr# input pci_gnt#[2:0] high isa bus interface isaoe# high low rmrtccs# hi-z first prefetch cycles when in isa or pcmcia mode. address start is 0xfffff0 la[23:17] unknown 0x00 sa[19:0] 0xfffxx 0xfff03 sd[15:0] unknown 0xff bhe#, memr# unknown high memw#, smemr#, smemw#, ior#, iow# unknown high ref# unknown high ale, aen low dack_enc[2:0] input 0x04 tc input low gpiocs# hi-z high rtcds#, rtcrw#, kbcs# hi-z rtcas unknown low pcmcia interface reset unknown high a[23:0] unknown 0x00 first prefetch cycles using rmrtccs# d[15:0] unknown 0xff iord#, iowr#, oe# unknown high we#, reg# high ce2#, ce1#, vcc5_en, vcc3_en high vpp_pgm, vpp_vcc low local bus interface pa[24:0] unknown first prefetch cycles pd[15:0] unknown 0xff prd# unknown high pbe#[1:0], fcs0#, fcs_0h# high
pin description 28/111 issue 1.0 - jul y 24, 2002 fcs_0l#, fcs1#, fcs_1h#, fcs_1l# high pwr#, iocs#[7:0] high ide controller dd[15:0] 0xff da[2:0] unknown low pcs1, pcs3, scs1, scs3 unknown low pdack#, sdack# high pdior#, pdiow#, sdior#, sdiow# high vga controller red, green, blue black vsync, hsync low col_sel unknown i2c interface scl / ddc[1] input sda / ddc[0] input tft interface tft[r,g,b][5:0] 0x00,0x00,0x00 tftline, tftframe low tftde, tftenvdd, tftenvcc, tftpwm low tftdclk oscillating at dclk speed usb interface usbdpls[1:0] 1 low usbdmns[1:0] 1 high poweron 1 unknown low serial controller txd0, rts0#, dtr0# high txd1, rts1#, dtr1# high keyboard & mouse interface kbclk, mclk low kbdata, mdata input parallel port pdir#, init# low strobe#, autofd# high slctin# unknown low ppd[7:0] unknown 0x00 gpio signals gpio[15:0] high jtag tdo high miscellaneous spkrd low table 2-5. signal value on reset signal name sysrsti# active sysrsti# inactive sysrsto# active release of sysrsto#
pin description issue 1.0 - july 24, 2002 29/111 table 2-6. pinout pin# pin name d15 sysrseti# c15 sysrseto# af21 xtali af22 xtalo af23 pci_clki af24 pci_clko e15 isa_clk a16 isa_clk2x ab18 osc14m ab24 hclk ab25 dev_clk 1 /fcs1# ac18 dclk af20 mclki af19 mclko u5 ma[0] v1 ma[1] v2 ma[2] v3 ma[3] v4 ma[4] v5 ma[5] w1 ma[6] w2 ma[7] w3 ma[8] w5 ma[9] y1 ma[10] y2 ba[0] u3 ras#[0] u4 ras#[1] r5 cas#[0] t1 cas#[1] r4 mwe# j4 md[0] j2 md[1] k5 md[2] k3 md[3] k1 md[4] l4 md[5] l2 md[6] m5 md[7] m3 md[8] m1 md[9] n4 md[10] n2 md[11] p1 md[12] p3 md[13] p5 md[14] r2 md[15] aa4 md[16] ab1 md[17] note 1 ; this signal is multiplexed see table 2-4 ab3 md[18] ac1 md[19] ac3 md[20] ad2 md[21] af3 md[22] ae4 md[23] af4 md[24] ad5 md[25] af5 md[26] ac6 md[27] af6 md[28] ac7 md[29] ae7 md[30] ab8 md[31] j3 md[32] j1 md[33] k4 md[34] k2 md[35] l5 md[36] l3 md[37] l1 md[38] m4 md[39] m2 md[40] n5 md[41] n3 md[42] n1 md[43] p2 md[44] p4 md[45] r1 md[46] r3 md[47] aa5 md[48] ab2 md[49] ab4 md[50] ac2 md[51] ad1 md[52] ae3 md[53] ad4 md[54] ac5 md[55] ab6 md[56] ae5 md[57] ab7 md[58] ad6 md[59] ae6 md[60] ad7 md[61] af7 md[62] ac8 md[63] u1 cs#[0] u2 cs#[1] y3 cs#[2]/ma[11] y4 cs#[3]/ma[12]/ba[1] t2 dqm[0] table 2-6. pinout pin# pin name note 1 ; this signal is multiplexed see table 2-4 t4 dqm[1] y5 dqm[2] aa2 dqm[3] t3 dqm[4] t5 dqm[5] aa1 dqm[6] aa3 dqm[7] b3 ad[0] a3 ad[1] c4 ad[2] b4 ad[3] a4 ad[4] d5 ad[5] c5 ad[6] b5 ad[7] a5 ad[8] d6 ad[9] c6 ad[10] b6 ad[11] a6 ad[12] e7 ad[13] d7 ad[14] c7 ad[15] a9 ad[16] e10 ad[17] c10 ad[18] b10 ad[19] a10 ad[20] e11 ad[21] d11 ad[22] c11 ad[23] a11 ad[24] e12 ad[25] d12 ad[26] c12 ad[27] b12 ad[28] a12 ad[29] e13 ad[30] d13 ad[31] e6 cbe[0] b7 cbe[1] b9 cbe[2] b11 cbe[3] c9 frame# e9 trdy# d9 irdy# b8 stop# a8 devsel# a7 par d8 perr# table 2-6. pinout pin# pin name note 1 ; this signal is multiplexed see table 2-4
pin description 30/111 issue 1.0 - jul y 24, 2002 e8 serr# c8 lock# c14 pci_req#[0] b14 pci_req#[1] a14 pci_req#[2] a13 pci_gnt#[0] b13 pci_gnt#[1] c13 pci_gnt#[2] c20 la[17] 1 b21 la[18] 1 b20 la[19] 1 e19 la[20] 1 e18 la[21] 1 c21 la[22] 1 d19 la[23] 1 p22 sa[0] 1 p23 sa[1] 1 p24 sa[2] 1 p25 sa[3] 1 p26 sa[4] 1 n26 sa[5] 1 n25 sa[6] 1 n24 sa[7] 1 n23 sa[8] 1 n22 sa[9] 1 m26 sa[10] 1 m25 sa[11] 1 m24 sa[12] 1 m23 sa[13] 1 m22 sa[14] 1 l26 sa[15] 1 l25 sa[16] 1 l24 sa[17] 1 l23 sa[18] 1 l22 sa[19] 1 k24 sd[0] 1 j26 sd[1] 1 j25 sd[2] 1 j24 sd[3] 1 k23 sd[4] 1 k22 sd[5] 1 h26 sd[6] 1 h25 sd[7] 1 h24 sd[8] 1 g26 sd[9] 1 g25 sd[10] 1 g24 sd[11] 1 j22 sd[12] 1 j23 sd[13] 1 f26 sd[14] 1 table 2-6. pinout pin# pin name note 1 ; this signal is multiplexed see table 2-4 f25 sd[15] 1 f23 iochrdy 1 d20 ale 1 k25 bhe# 1 f24 memr# 1 a22 memw# 1 g23 smemr# 1 e21 smemw# 1 h22 ior# 1 e26 iow# 1 e25 master# 1 e24 mcs16# 1 c22 iocs16# 1 g22 ref# 1 e17 aen 1 a23 iochck# 1 u25 rtcrw# 1 u26 rtcds# 1 u24 rtcas 1 /fcs0# u23 rmrtccs# 1 d22 gpiocs# 1 d24 irq_mux[0] e23 irq_mux[1] c26 irq_mux[2] f22 irq_mux[3] a24 dack_enc[0] c23 dack_enc[1] 1 b23 dack_enc[2] 1 d26 dreq_mux[0] 1 d25 dreq_mux[1] 1 b24 tc 1 b15 pci_int#[0] a15 pci_int#[1] e14 pci_int#[2] d14 pci_int#[3] b16 isaoe# 1 b22 kbcs# 1 k26 zws# 1 r23 pirq r24 sirq t22 pdrq t23 sdrq r25 pdack# r26 sdack# t25 pdior# t24 pdiow# r22 sdior# t26 sdiow# d18 pa[22] table 2-6. pinout pin# pin name note 1 ; this signal is multiplexed see table 2-4 c19 pa[23] b19 pa[24] a17 fcs_0h b17 fcs_0l c16 fcs_1h e16 fcs_1l d17 iocs#[4] c18 iocs#[5] b18 iocs#[6] c17 iocs#[7] ad8 red af8 green ac9 blue ab10 vsync af9 hsync ab9 vref_dac ad9 rset ae8 comp ae9 vdd_dac ac10 vss_dac ab15 vclk af16 vin[0] ae16 vin[1] ac16 vin[2] ab16 vin[3] af17 vin[4] ae17 vin[5] ad17 vin[6] ab17 vin[7] ad18 odd_even# af18 vcs ae10 tftr0 af10 tftr1 ab11 tftr2 ad11 tftr3 ae11 tftr4 af11 tftr5 ab12 tftg0 ac12 tftg1 ad12 tftg2 ae12 tftg3 af12 tftg4 ab13 tftg5 ac13 tftb0 ad13 tftb1 ae13 tftb2 af13 tftb3 af14 tftb4 table 2-6. pinout pin# pin name note 1 ; this signal is multiplexed see table 2-4
pin description issue 1.0 - july 24, 2002 31/111 ae14 tftb5 ab14 tftline ac14 tftframe af15 tftde ae15 tftenvdd ad15 tftenvcc ac15 tftpwm ad14 tftdclk d21 oc a20 usbdmns[0] a18 usbdmns[1] a21 usbdpls[0] a19 usbdpls[1] e20 poweron ac22 cts0# ac24 cts1# ad21 dcd0# ae24 dcd1# ac21 dsr0# ad25 dsr1# ad22 dtr0# ac26 dtr1# ad23 ri0# aa22 ri1# ae22 rts0# ac25 rts1# ab21 rxd0 ad26 rxd1 ae23 txd0 ab23 txd1 ad20 kbclk ab19 kbdata ac20 mdata ab20 mclk aa23 pe w24 slct w23 busy w25 err# w26 ack# v22 pddir v24 strobe# v25 init# v26 autofd# u22 slctin# y22 ppd[0] aa24 ppd[1] aa25 ppd[2] table 2-6. pinout pin# pin name note 1 ; this signal is multiplexed see table 2-4 aa26 ppd[3] y24 ppd[4] y25 ppd[5] y26 ppd[6] w22 ppd[7] ac19 scl / ddc[1] ad19 sda / ddc[0] c2 gpio[0] c1 gpio[1] d3 gpio[2] d2 gpio[3] d1 gpio[4] e4 gpio[5] e3 gpio[6] e2 gpio[7] e1 gpio[8] f5 gpio[9] f4 gpio[10] f3 gpio[11] f2 gpio[12] g5 gpio[13] g4 gpio[14] g2 gpio[15] h2 tclk j5 trst h5 tdi h3 tms h1 tdo g1 scan_enable ad10 col_sel c25 spkrd ad16 vdd_dclk_pll y23 vdd_devclk_pll ae20 vdd_hclki_pll ab26 vdd_hclko_pll ae19 vdd_mclki_pll ae18 vdd_mclko_pll ae21 vdd_pciclk_pll f13 vdd_core f15 vdd_core f17 vdd_core k6 vdd_core m21 vdd_core n6 vdd_core p21 vdd_core table 2-6. pinout pin# pin name note 1 ; this signal is multiplexed see table 2-4 r6 vdd_core u21 vdd_core aa10 vdd_core aa12 vdd_core aa14 vdd_core a2 vdd a25 vdd b1 vdd b26 vdd f7 vdd f11 vdd f20 vdd g6 vdd g21 vdd h6 vdd j21 vdd k21 vdd u6 vdd v6 vdd y6 vdd y21 vdd aa7 vdd aa16 vdd aa18 vdd aa20 vdd ae01 vdd ae26 vdd af02 vdd af25 vdd a1 gnd a26 gnd b2 gnd b25 gnd c3 gnd c24 gnd d4 gnd d10 gnd d16 gnd d23 gnd e5 gnd e22 gnd f6 gnd f8 gnd f9 gnd f10 gnd f12 gnd f14 gnd f16 gnd f18 gnd table 2-6. pinout pin# pin name note 1 ; this signal is multiplexed see table 2-4
pin description 32/111 issue 1.0 - jul y 24, 2002 f19 gnd f21 gnd h4 gnd h21 gnd h23 gnd j6 gnd l6 gnd l11:16 gnd l21 gnd m6 gnd m11:16 gnd n11:16 gnd n21 gnd p6 gnd p11:16 gnd r11:16 gnd r21 gnd t6 gnd table 2-6. pinout pin# pin name note 1 ; this signal is multiplexed see table 2-4 t11:16 gnd t21 gnd v21 gnd v23 gnd w4 gnd w6 gnd w21 gnd aa6 gnd aa8 gnd aa9 gnd aa11 gnd aa13 gnd aa15 gnd aa17 gnd aa19 gnd aa21 gnd ab5 gnd ab22 gnd table 2-6. pinout pin# pin name note 1 ; this signal is multiplexed see table 2-4 ac4 gnd ac11 gnd ac17 gnd ac23 gnd ad3 gnd ad24 gnd ae2 gnd ae25 gnd af1 gnd af26 gnd g3 reserved f1 reserved table 2-6. pinout pin# pin name note 1 ; this signal is multiplexed see table 2-4
strap option issue 1.0 - july 24, 2002 33/ 111 3. strap option this chapter defines the stpc atlas strap options and their locations. some strap options are left programmable for future versions of silicon. the strap options are sampled at a specific point of the boot process. this is shown in detail in figure 4-3 signal designation location actual settings set to 0 set to 1 md1 reserved 2 not accessible pull up - - md2 hclk speed index 5f,bit 6 user defined see section 3.1.3. md3 index 5f,bit 7 user defined md[4] pci_clko divisor index 4a,bit 1 pull-up see section 3.1.1. md[5] mclk synchro (see section 3.1.1. ) index 4a,bit 2 user defined async sync md[6] pci_clko programming index 4a,bit 6 user defined see section 3.1.1. md[7] index 4a,bit 7 pull-down md[8] isa / pcmcia / local bus index 4a,bit 3 user defined see section 3.1.1. md[9] index 4a,bit 3 user defined md10 reserved 2 index 4b,bit 2 pull down - - md11 reserved 2 index 4b,bit 3 pull down - - md14 cpu clock multiplication index 4b,bit 6 pull-up see section 3.1.2. md15 reserved 2 not accessible pull up - - md16 reserved 2 not accessible pull up - - md17 pci_clko divisor index 4a,bit 0 user defined see section 3.1.1. md18 hclk pad direction index 4c,bit 2 pull-up input output md19 mclk pad direction index 4c,bit 3 pull-up hi-z output md20 dclk pad direction index 4c,bit 4 user defined input output md21 reserved 2 index 5f,bit 0 pull up - - md23 reserved 2 index 5f,bit 2 pull up - - md24 hclk pll speed index 5f,bit 3 user defined see section 3.1.3. md25 index 5f,bit 4 user defined md26 index 5f,bit 5 user defined md27 reserved 2 not accessible pull up - - md28 reserved 2 not accessible pull up - - md29 reserved 2 not accessible pull up - - md30 reserved 2 not accessible pull up - - md31 reserved 2 not accessible pull up md32 reserved 2 not accessible pull down md33 reserved 2 not accessible pull up md34 reserved 2 not accessible pull down md35 reserved 2 not accessible pull down md36 local bus boot device size index 4b,bit 0 user defined 8-bit 16-bit md37 reserved 2 not accessible pull down - - md38 reserved 2 not accessible pull down - - md40 cpu clock multiplication index 4b,bit 7 user defined see section 3.1.2. md41 reserved 2 not accessible pull down - - md42 reserved 2 not accessible pull up - - md 43 reserved 2 not accessible pull down - - note 1 : strap options on tc/pa[3] and dack_enc[2:0]/pa[2:0] are required for all the stpc atlas configurations (isa, pcmcia, local bus). note 2 : must be implemented.
strap option 34/ 111 issue 1.0 - jul y 24, 2002 md 45 cpuclk/hckl deskew programming not accessible user defined see section 3.1.5. md 46 not accessible user defined md 47 reserved 2 not accessible pull down - - md 48 reserved 2 not accessible pull up - - md 50 internal uart2 (see section 3.1.4. ) index 4c,bit 0 user defined disable enable md 51 internal uart1 (see section 3.1.4. ) index 4c,bit 1 user defined disable enable md 52 internal kbd / mouse (see section 3.1.4. ) index 4c,bit 6 user defined disable enable md 53 internal parallel port (see section 3.1.4. ) index 4c,bit 7 user defined disable enable tc 1 reserved 2 hardware pull up - - dack_enc[2] 1 reserved 2 hardware pull up - - dack_enc[1] 1 reserved 2 hardware pull up - - dack_enc[0] 1 reserved 2 hardware pull up - - signal designation location actual settings set to 0 set to 1 note 1 : strap options on tc/pa[3] and dack_enc[2:0]/pa[2:0] are required for all the stpc atlas configurations (isa, pcmcia, local bus). note 2 : must be implemented.
strap option issue 1.0 - july 24, 2002 35/ 111 3.1. strap option register description 3.1.1. strap register 0 this register is read only. strap0 access = 0022h/0023h regoffset =04ah 76543210 md[7] md[6] md[9] md[8] rsv md[5] md[4] md[17] this register defaults to the values sampled on the md pins after reset bit number sampled mnemonic description bits 7-6 md[7:6] pciclk pll set-up: the value sampled on md[7:6] controls the pciclk pll programming according to the pciclk frequency. md7 md6 0 0 pciclk frequency between 16 & 32 mhz 0 1 pciclk frequency between 32 & 64 mhz 1 x reserved bits 5-4 md[9:8] mode selection: md9 md8 0 0 isa mode: isa enabled, pcmcia & local bus disabled 0 1 pcmcia mode: pcmcia enabled, isa & local bus disabled 1 0 local bus mode: local bus enabled, isa & pcmcia disabled 1 1 reserved bit 3 rsv reserved bit 2 md[5] host memory synchronization. this bit reflects the value sampled on [md5] and controls the mclk/hclk synchronization. 0: mclk and hclk not synchronized 1: mclk and hclk synchronized. bits 1-0 md[4], md[17] pciclk division: these bits reflect the values sampled on [md4] and md[17] to select the pciclk frequency. md4 md17 0 x pci clock output = hclk / 4 1 0 pci clock output = hclk / 3 1 1 pci clock output = hclk / 2
strap option 36/ 111 issue 1.0 - jul y 24, 2002 3.1.2. strap register 1 this register is read only. strap1 access = 0022h/0023h regoffset =04bh 76543210 md[40] md[14] rsv rsv rsv rsv rsv md[36] this register defaults to the values sampled on the md pins after reset bit number sampled mnemonic description bits 7-6 md[40] & md[14] cpu clock multiplication (486 mode): md14 md40 1 0 x 1 1 1 x 2 all other settings are reserved hclk maximum speed is 66mhz and in cpu mode x2. operation in x1 mode is only guaranteed up to 66mhz. bits 5-1 rsv reserved bit 0 md[36] these bits reflect the values sampled on md[36] and determines the local bus boot device width: 0: 8-bit boot device 1: 16-bit boot device
strap option issue 1.0 - july 24, 2002 37/ 111 3.1.3. hclk pll strap register this register is read only. hclk_strap0 access = 0022h/0023h regoffset =05fh 76543210 rsv md[26] md[25] md[24] rsv this register defaults to the values sampled on the md pins after reset bit number sampled mnemonic description bits 7-6 rsv these bits are fixed to 0 bits 5-3 md[26:24] these pins reflect the values sampled on md[26:24] pins respectively and control the host clock frequency synthesizer as shown in table 3-1 bits 2-0 rsv reserved table 3-1. hclk fre q uenc y confi g uration md[3] md[2] md[26] md[25] md[24] hclk speed 0000025 mhz 0000150 mhz 0001060 mhz 0001166 mhz all other settings are reserved
strap option 38/ 111 issue 1.0 - jul y 24, 2002 3.1.4. strap register 2 this register is read only with the exception of bit 4 strap2 access = 0022h/0023h regoffset =04ch 76543210 md[53] md[52] rsv md[20] md[19] md[18] md[51] md[50] this register defaults to the values sampled on the md pins after reset bit number sampled mnemonic description bit 7 md[53] this bit reflects the value sampled on md[53] pin and determines whether the internal parallel port controller is used 0: internal parallel port controller is disabled 1: internal parallel port controller is enabled bit 6 md[52] this bit reflects the value sampled on md[52] pin and determines whether the internal keyboard controller is used 0: internal keyboard controller is disabled 1: internal keyboard controller is enabled bit 5 rsv reserved bit 4 md[20] this bit reflects the value sampled on md[20] pin and controls the dot clock pin (dclk) direction as follows: 0: input. 1: output of the internal frequency synthesizer dclk pll. bit 3 md[19] this bit reflects the value sampled on md[19] pin and controls the memory clock output pin (mclko) as follows: 0: tristated. 1: output of the internal frequency synthesizer mclko pll. bit 2 md[18] this bit reflects the value sampled on md[18] pin and controls the host clock pin (hclk) direction as follows: 0: input. 1: output of the internal frequency synthesizer hclk pll. bit 1 md[51] this bit reflects the value sampled on md[51] pin and determines whether the internal uart1 is enabled: 0: internal uart1 is disabled 1: internal uart1 is enabled bit 0 md[50] this bit reflects the value sampled on md[50] pin and determines whether the internal uart2 is enabled: 0: internal uart2 is disabled 1: internal uart2 is enabled
strap option issue 1.0 - july 24, 2002 39/ 111 3.1.5. cpuclk/hckl deskew programming ; note that these straps are not accessible by software. md[45] md[46] description 10 hclk between 33mhz and 64mhz 01 hclk between 64mhz and 133mhz all other settings are reserved table 3-1.
strap option 40/ 111 issue 1.0 - jul y 24, 2002 3.2. typical strap option implementation table table 3-1. shows the detailed strap options required to boot the stpc in isa mode with a host clock frequency of 66mhz in x2 mode with internal keyboard/mouse, uarts and parallel port enabled. signal designation actual settings description md1 reserved 2 pull up - md2 hclk speed pull down hclk = 66mhz md3 pull down md[4] pci_clko divisor pull up pciclk = hclk/2 md[5] mclk synchro (see section 3.1.1. ) pull down asynchronous md[6] pci_clko programming pull up pciclk pll window = 32mhz - 64mhz md[7] pull down md[8] isa / pcmcia / local bus pull down isa mode md[9] pull down md10 reserved 2 pull down - md11 reserved 2 pull down - md14 cpu clock multiplication pull up x2 mode md15 reserved 2 pull up - md16 reserved 2 pull up - md17 pci_clko divisor pull up pciclk = hclk/2 md18 hclk pad direction pull up output md19 mclk pad direction pull up output md20 dclk pad direction pull up output md21 reserved 2 pull up - md23 reserved 2 pull up - md24 hclk pll speed pull up hclk = 66mhz md25 pull up md26 pull down md27 reserved 2 pull up - md28 reserved 2 pull up - md29 reserved 2 pull up - md30 reserved 2 pull up - md31 reserved 2 pull up md32 reserved 2 pull down md33 reserved 2 pull up md34 reserved 2 pull down md35 reserved 2 pull down md36 local bus boot device size user defined not applicable md37 reserved 2 pull down - md38 reserved 2 pull down - md40 cpu clock multiplication pull up x2 mode md41 reserved 2 pull down - md42 reserved 2 pull up - md 43 reserved 2 pull down - note 1 : strap options on tc/pa[3] and dack_enc[2:0]/pa[2:0] are required for all the stpc atlas configurations (isa, pcmcia, local bus). note 2 : must be implemented. table 3-1. typical strap option implementation
strap option issue 1.0 - july 24, 2002 41/ 111 md 45 cpuclk/hckl deskew programming pull down hclk between 64mhz and 133mhz md 46 pull up md 47 reserved 2 pull down - md 48 reserved 2 pull up - md 50 internal uart2 (see section 3.1.4. ) pull up enable md 51 internal uart1 (see section 3.1.4. ) pull up enable md 52 internal kbd / mouse (see section 3.1.4. ) pull up enable md 53 internal parallel port (see section 3.1.4. ) pull up enable tc 1 reserved 2 pull up - dack_enc[2] 1 reserved 2 pull up - dack_enc[1] 1 reserved 2 pull up - dack_enc[0] 1 reserved 2 pull up - signal designation actual settings description note 1 : strap options on tc/pa[3] and dack_enc[2:0]/pa[2:0] are required for all the stpc atlas configurations (isa, pcmcia, local bus). note 2 : must be implemented. table 3-1. typical strap option implementation
strap option 42/ 111 issue 1.0 - jul y 24, 2002
electrical specifications issue 1.0 - july 24, 2002 43/111 4. electrical specifications 4.1. introduction the electrical specifications in this chapter are valid for the stpc atlas. 4.2. electrical connections 4.2.1. power/ground connections/ decoupling due to the high frequency of operation of the stpc atlas, it is necessary to install and test this device using standard high frequency techniques. the high clock frequencies used in the stpc atlas and its output buffer circuits can cause transient power surges when several output buffers switch output levels simultaneously. these effects can be minimized by filtering the dc power leads with low-inductance decoupling capacitors, using low impedance wiring, and by utilizing all of the vss and vdd pins. 4.2.2. unused input pins no unused input pin should be left unconnected unless they have an integrated pull-up or pull- down. connect active-low inputs to vdd through a 20 k w (10%) pull-up resistor and active-high inputs to vss. for bi-directionnal active-high inputs, connect to vss through a 20 k w (10%) pull-up resistor to prevent spurious operation. 4.2.3. reserved designated pins pins designated as reserved should be left dis- connected. connecting a reserved pin to a pull-up resistor, pull-down resistor, or an active signal could cause unexpected results and possible circuit malfunctions. 4.3. absolute maximum ratings the following table lists the absolute maximum ratings for the stpc atlas device. stresses beyond those listed under table 4-1 limits may cause permanent damage to the device. these are stress ratings only and do not imply that operation under any conditions other than those specified in section "operating conditions". exposure to conditions beyond those outlined in table 4-1 may (1) reduce device reliability and (2) result in premature failure even when there is no immediately apparent sign of failure. prolonged exposure to conditions at or near the absolute maximum ratings ( table 4-1 ) may also result in reduced useful life and reliability. 4.3.1. 5v tolerance the stpc is capable of running with i/o systems that operate at 5 v such as pci and isa devices. certain pins of the stpc tolerate inputs up to 5.5 v. above this limit the component is likely to sustain permanent damage. all 5 volt tolerant pins are outlined in table 2-3 buffer type descriptions . note 1: the figures specified apply to the tcase of a stpc device that is soldered to a board, as detailed in the design guidelines section, for commercial and in- dustrial temperature ranges. table 4-1. absolute maximum ratings symbol parameter minimum maximum units v ddx dc supply voltage -0.3 4.0 v v core dc supply voltage for core -0.3 2.7 v v i , v o digital input and output voltage -0.3 vdd + 0.3 v v 5t 5volt tolerance -0.3 5.5 v v esd esd capacity (human body mode) - 2000 v t stg storage temperature -40 +150 c t oper operating temperature (note 1) 0 +85 c -40 +115 c p tot maximum power dissipation (package) - 4.8 w
electrical specifications 44/111 issue 1.0 - jul y 24, 2002 4.4. dc characteristics table 4-2. dc characteristics symbol parameter test conditions min typ max unit v dd 3.3v operating voltage 3.0 3.3 3.6 v v core 2.5v operating voltage 2.45 2.5 2.7 v p dd 3.3v supply power 3.0v < v dd < 3.6v 0.24 w p core 2.5v supply power 1 2.45v < v core < 2.7v 4.1 w v il input low voltage except xtali -0.3 0.8 v xtali -0.3 0.8 v v ih input high voltage except xtali 2.1 v dd +0.3 v xtali 2.35 v dd +0.3 v i lk input leakage current input, i/o -5 5 m a integrated pull up/down 50 k w note 1; power consumption is heavily dependant on the clock frequencies and on the enabled features. see details in table 4-5 to table 4-8 . table 4-3. pad buffers dc characteristics buffer type i/o count v ih min (v) v il max (v) v oh min (v) v ol max (v) i ol min (ma) i oh max (ma) c load max (pf) derating (ps/pf) 1 c in (pf) ana 10 2.35 0.9 - - - - - - - osci13b 2 2.1 0.8 2.4 0.4 2 - 2 50 - - bt4crp 1 - - 0.85*v dd 0.4 4 - 4 100 30 5.61 bt8trp_tc 7 - - 2.4 0.4 8 - 8 200 21 6.89 bd4strp_ft 64 2 0.8 2.4 0.4 4 - 4 100 42 5.97 bd4strup_ft 14 2 0.8 2.4 0.4 4 - 4 100 41 5.97 bd4strp_tc 26 2 0.8 2.4 0.4 4 - 4 100 42 5.83 bd8strp_ft 30 2 0.8 2.4 0.4 8 - 8 200 23 5.96 bd8strup_ft 47 2 0.8 2.4 0.4 8 - 8 200 23 5.96 bd8strp_tc 12 2 0.8 2.4 0.4 8 - 8 200 21 7.02 bd8trp_tc 53 2 0.8 2.4 0.4 8 - 8 200 21 7.03 bd8pciarp_ft 50 0.5*v dd 0.3*v dd 0.9*v dd 0.1*v dd 1.5 - 0.5 200 15 6.97 bd14starp_ft 18 2 0.8 2.4 0.4 14 -14 100 71 6.20 bd16staruqp_tc 19 2 0.8 2.4 0.4 16 -16 400 12 9.34 schmitt_ft 1 2 0.8 - - - - - - 5.97 tlcht_ft 16 2 0.8 - - - - - - 5.97 tlcht_tc 1 2 0.8 - - - - - - 5.97 tlchtd_tc 1 2 0.8 - - - - - - 5.97 tlchtu_tc 1 2 0.8 - - - - - - 5.97 usbds_2v5 (slow) 4 2 0.8 2.4 0.4 - - 100 45.2 8.41 usbds_2v5 (fast) 98.8 note 1: time to output variation depending on the capacitive load. table 4-4. ramdac dc specification symbol parameter min max vref_dac voltage reference 1.00 v 1.24 v inl integrated non linear error - 3 lsb dnl differentiated non linear error - 1 lsb blc black level current 1.0 ma 2.0 ma
electrical specifications issue 1.0 - july 24, 2002 45/111 note 1: pci clock at 33mhz wlc white level current 15.00 ma 18.50 ma table 4-4. ramdac dc specification symbol parameter min max table 4-5. vga ramdac power consumption dclk (mhz) dac mode (state) p max (mw) vdd_dac = 2.45v vdd_dac = 2.7v - shutdown 0 0 6.25 - 135 active 150 180 table 4-6. 2.5v power consumptions (v core + vdd_x_pll + vdd_dac) hclk (mhz) cpuclk (mhz) mclk (mhz) mode dclk (mhz) pmu (state) p max (w) v 2.5v =2.45v v 2.5v =2.7v 66 133 (x2) 66 sync stopped stop clock 1.5 1.9 full speed 2.5 3.0 135 stop clock 2.1 2.6 full speed 2.1 3.6 66 133 (x2) 90 async stopped stop clock 1.9 2.4 full speed 2.8 3.5 135 stop clock 2.5 3.1 full speed 3.3 4.1 table 4-7. 3.3v power consumptions (v dd ) hclk (mhz) cpuclk (mhz) mclk (mhz) dclk (mhz) pmu (state) p max (mw) 66 133 (x2) 66 6.26 full speed 130 135 215 66 133 (x2) 90 6.26 full speed 150 135 240 table 4-8. pll power consumptions pll name p max (mw) vdd_pll = 2.45v vdd_pll = 2.7v vdd_dclk_pll 5 10 vdd_devclk_pll 5 10 vdd_hclki_pll 5 10 vdd_hclko_pll 5 10 vdd_mclki_pll 5 10 vdd_mclko_pll 5 10 vdd_pciclk_pll 5 10
electrical specifications 46/111 issue 1.0 - jul y 24, 2002 4.5. ac characteristics this section lists the ac characteristics of the stpc interfaces including output delays, input setup requirements, input hold requirements and output float delays. these measurements are based on the measurement points identified in figure 4-1 and figure 4-2 . the rising clock edge reference level vref and other reference levels are shown in table 4-9 below. input or output signals must cross these levels during testing. figure 4-1 shows output delay (a and b) and input setup and hold times (c and d). input setup and hold times (c and d) are specified minimums, defining the smallest acceptable sampling window a synchronous input signal must be stable for correct operation. note: refer to figure 4-1 . table 4-9. drive level and measurement points for switching characteristics symbol value units v ref 1.5 v v ihd 2.5 v v ild 0.0 v figure 4-1. drive level and measurement points for switching characteristics clk: v ref v ild v ihd tx legend: a - maximum output delay specification b - minimum output delay specification c - minimum input setup specification d - minimum input hold specification v ref valid valid valid outputs: inputs: output n output n+1 input max min a b cd v ref v ild v ihd
electrical specifications issue 1.0 - july 24, 2002 47/111 figure 4-2. clk timing measurement points clk t5 t4 t3 v ref v il (max) v ih (min) t2 t1 legend: t1 - one clock cycle t2 - minimum time at v ih t3 - minimum time at v il t4 - clock fall time t5 - clock rise time note; all signals are sampled on the rising edge of the clk.
electrical specifications 48/111 issue 1.0 - jul y 24, 2002 4.5.1. power on sequence figure 4-3 describes the power-on sequence of the stpc, also called cold reset. there is no dependency between the different power supplies and there is no constraint on their rising time. sysrsti# as no constraint on its rising edge but must stay active until power supplies are all within specifications, a margin of 10 m s is even recommended to let the stpc plls and strap options stabilize. strap options are continuously sampled during sysrsti# low and must remain stable. once sysrsti# is high, they must not change until sysrsto# goes high. bus activity starts only few clock cycles after the release of sysrsto#. the t oggling signals depend on the stpc configuration. in isa mode, activity is visible on pci prior to the isa bus as the controller is part of the south bridge. in local bus mode, the pci bus is not accessed and the flash chip select is the control signal to monitor. figure 4-3. power-on timing diagram strap options power supplies sysrsti# sysrsto# 14 mhz 1.6 v valid configuration > 10 us hclk pci_clk 2.3 ms isaclk
electrical specifications issue 1.0 - july 24, 2002 49/111 4.5.2 reset sequence figure 4-4 describes the reset sequence of the stpc, also called warm reset. the constraints on the strap options and the bus activities are the same as for the cold reset. the sysrsti# pulse duration must be long enough to have all the strap options stabilized and must be adjusted depending on resistor values. it is mandatory to have a clean reset pulse without glitches as the stpc could then sample invalid strap option setting and enter into an umpredicta- ble mode. while sysrsti# is active, the pci clock pll runs in open loop mode at a speed of few 100s khz. fi g ure 4-4. reset timin g dia g ram strap options sysrsti# sysrsto# 14 mhz valid configuration hclk pci_clk 2.3 ms isaclk 1.6 v md[63:0]
electrical specifications 50/111 issue 1.0 - jul y 24, 2002 4.5.3. sdram interface figure 4-5 , table 4-10 , table 4-11 lists the ac characteristics of the sdram interface. the mclkx clocks are the input clock of the sdram devices. the pc100 memory is recommended to reach 90mhz operation. figure 4-5. sdram timing diagram mclki stpc.output stpc.input mclkx t delay t setup t hold t output (min) t output (max) t cycle t high t low table 4-10. sdram bus ac timings - commercial temperature range name parameter min typ max unit tcycle mclki cycle time 10 ns thigh mclki high time 4 ns tlow mclki low time 4 ns mclki rising time 1 ns mclki falling time 1 ns tdela y mclkx to mclki dela y 2.1 ns toutput mclki to ras# valid 1.6 5.2 ns mclki to cas# valid 1.6 5.2 ns mclki to cs# valid 1.6 5.2 ns mclki to dqm[ ] outputs valid 1.35 5.2 ns mclki to md[ ] outputs valid 1.35 5.2 ns mclki to ma[ ] outputs valid 1.6 5.2 ns mclki to mwe# valid 1.6 5.2 ns tsetup md[63:0] setup to mckli 7.5 ns thold md[63:0] hold from mckli -0.36 ns note: these timings are for a load of 50pf, part running at 100mhz and readclk not activated
electrical specifications issue 1.0 - july 24, 2002 51/111 the pc100 memory is recommended to reach 90mhz operation. table 4-11. sdram bus ac timings - industrial temperature range name parameter min typ max unit tcycle mclki cycle time 11 ns thigh mclki high time 4 ns tlow mclki low time 4 ns mclki rising time 1 ns mclki falling time 1 ns tdelay mclkx to mclki delay 1.8 ns toutput mclki to ras# valid 1.7 6.5 ns mclki to cas# valid 1.7 6.5 ns mclki to cs# valid 1.7 6 ns mclki to dqm[ ] outputs valid 26ns mclki to md[ ] outputs valid 27.8ns mclki to ma[ ] outputs valid 1.7 6.5 ns mclki to mwe# valid 1.7 6 ns tsetup md[63:0] setup to mckli 7.5 ns thold md[63:0] hold from mckli -0.36 ns note: these timings are for a load of 50pf, part running at 90mhz and readclk not activated
electrical specifications 52/111 issue 1.0 - jul y 24, 2002 4.5.4. pci interface figure 4-6 and table 4-12 list the ac characteris- tics of the pci interface. pciclkx stands for any pci device clock input. figure 4-6. pci timing diagram pciclki stpc.output stpc.input pciclkx t clkx t setup t hold t output (min) t output (max) t cycle t high t low hclk t hclk table 4-12. pci bus ac timings name parameter min typ max unit hclk to pciclko delay (md[30:27] = 1111) 4.4 5.0 5.7 ns thclk hclk to pciclki delay 6.5 7.5 8.5 ns tclkx pciclki to pciclkx skew -0.5 0.3 1.0 ns tcycle pciclki cycle time 30 ns thigh pciclki high time 13 ns tlow pciclki low time 13 ns pciclki rising time 1.5 ns pciclki falling time 1.5 ns pciclki to an y output -ns setup to pciclki --ns hold from pciclki --ns hclk to an y output -ns setup to hclk --ns hold from hclk --ns note: these timings are for a load of 50pf.
electrical specifications issue 1.0 - july 24, 2002 53/111 4.5.5 ipc interface table 4-13 lists the ac characteristics of the ipc interface. figure 4-7. ipc timing diagram isaclk irq_mux[3:0] dreq_mux[1:0] isaclk2x t dly t setup t setup table 4-13. ipc interface ac timings name parameter min max unit t dly isaclk2x to isaclk delay ns isaclk2x to dack_enc[2:0] valid ns isaclk2x to tc valid ns t setup irq_mux[3:0] input setup to isaclk2x 0 - ns t setup dreq_mux[1:0] input setup to isaclk2x 0 - ns
electrical specifications 54/111 issue 1.0 - jul y 24, 2002 4.5.6 isa interface ac timing characteristics table 4-8 and table 4-14 list the ac characteris- tics of the isa interface. figure 4-8 isa cycle (ref table 4-14 ) note 1: stands for smemr#, smemw#, memr#, memw#, ior# & iow#. the clock has not been represented as it is dependent on the isa slave mode. valid aenx valid address valid address, sbhe* v.dat a valid data 54 28 26 64 59 58 55 28 23 61 48 47 26 23 57 27 24 42 41 10 11 34 33 3 22 56 29 25 9 18 2 12 38 37 15 14 13 12 ale aen la [23:17] sa [19:0] control (note 1) iocs16# mcs16# iochrdy read data write data table 4-14. isa bus ac timing name parameter min max units 2 la[23:17] valid before ale# negated 5t cycles 3 la[23:17] valid before memr#, memw# asserted 3a memory access to 16-bit isa slave 5t cycles 3b memory access to 8-bit isa slave 5t cycles 9 sa[19:0] & sbhe valid before ale# negated 1t cycles 10 sa[19:0] & sbhe valid before memr#, memw# asserted 10a memory access to 16-bit isa slave 2t cycles 10b memory access to 8-bit isa slave 2t cycles 10 sa[19:0] & shbe valid before smemr#, smemw# asserted 10c memory access to 16-bit isa slave 2t cycle note: the si g nal numberin g refers to table 4-8
electrical specifications issue 1.0 - july 24, 2002 55/111 10d memory access to 8-bit isa slave 2t cycle 10e sa[19:0] & sbhe valid before ior#, iow# asserted 2t cycles 11 isaclk2x to iow# valid 11a memory access to 16-bit isa slave - 2bclk 2t cycles 11b memory access to 16-bit isa slave - standard 3bclk 2t cycles 11c memory access to 16-bit isa slave - 4bclk 2t cycles 11d memory access to 8-bit isa slave - 2bclk 2t cycles 11e memory access to 8-bit isa slave - standard 3bclk 2t cycles 12 ale# asserted before ale# negated 1t cycles 13 ale# asserted before memr#, memw# asserted 13a memory access to 16-bit isa slave 2t cycles 13b memory access to 8-bit isa slave 2t cycles 13 ale# asserted before smemr#, smemw# asserted 13c memory access to 16-bit isa slave 2t cycles 13d memory access to 8-bit isa slave 2t cycles 13e ale# asserted before ior#, iow# asserted 2t cycles 14 ale# asserted before al[23:17] 14a non compressed 15t cycles 14b compressed 15t cycles 15 ale# asserted before memr#, memw#, smemr#, smemw# negated 15a memory access to 16-bit isa slave- 4 bclk 11t cycles 15e memory access to 8-bit isa slave- standard cycle 11t cycles 18a ale# negated before la[23:17] invalid (non compressed) 14t cycles 18a ale# negated before la[23:17] invalid (compressed) 14t cycles 22 memr#, memw# asserted before la[23:17] 22a memory access to 16-bit isa slave. 13t cycles 22b memory access to 8-bit isa slave. 13t cycles 23 memr#, memw# asserted before memr#, memw# negated 23b memory access to 16-bit isa slave standard cycle 9t cycles 23e memory access to 8-bit isa slave standard cycle 9t cycles 23 smemr#, smemw# asserted before smemr#, smemw# negated 23h memory access to 16-bit isa slave standard cycle 9t cycles 23l memory access to 16-bit isa slave standard cycle 9t cycles 23 ior#, iow# asserted before ior#, iow# negated 23o memory access to 16-bit isa slave standard cycle 9t cycles 23r memory access to 8-bit isa slave standard cycle 9t cycles 24 memr#, memw# asserted before sa[19:0] 24b memory access to 16-bit isa slave standard cycle 10t cycles 24d memory access to 8-bit isa slave - 3blck 10t cycles 24e memory access to 8-bit isa slave standard cycle 10t cycles 24f memory access to 8-bit isa slave - 7bclk 10t cycles 24 smemr#, smemw# asserted before sa[19:0] 24h memory access to 16-bit isa slave standard cycle 10t cycles 24i memory access to 16-bit isa slave - 4bclk 10t cycles 24k memory access to 8-bit isa slave - 3bclk 10t cycles 24l memory access to 8-bit isa slave standard cycle 10t cycles table 4-14. isa bus ac timing name parameter min max units note: the signal numbering refers to table 4-8
electrical specifications 56/111 issue 1.0 - jul y 24, 2002 24 ior#, iow# asserted before sa[19:0] 24o i/o access to 16-bit isa slave standard cycle 19t cycles 24r i/o access to 16-bit isa slave standard cycle 19t cycles 25 memr#, memw# asserted before next ale# asserted 25b memory access to 16-bit isa slave standard cycle 10t cycles 25d memory access to 8-bit isa slave standard cycle 10t cycles 25 smemr#, smemw# asserted before next ale# asserted 25e memory access to 16-bit isa slave - 2bclk 10t cycles 25f memory access to 16-bit isa slave standard cycle 10t cycles 25h memory access to 8-bit isa slave standard cycle 10t cycles 25 ior#, iow# asserted before next ale# asserted 25i i/o access to 16-bit isa slave standard cycle 10t cycles 25k i/o access to 16-bit isa slave standard cycle 10t cycles 26 memr#, memw# asserted before next memr#, memw# asserted 26b memory access to 16-bit isa slave standard cycle 12t cycles 26d memory access to 8-bit isa slave standard cycle 12t cycles 26 smemr#, smemw# asserted before next smemr#, smemw# asserted 26f memory access to 16-bit isa slave standard cycle 12t cycles 26h memory access to 8-bit isa slave standard cycle 12t cycles 26 ior#, iow# asserted before next ior#, iow# asserted 26i i/o access to 16-bit isa slave standard cycle 12t cycles 26k i/o access to 8-bit isa slave standard cycle 12t cycles 28 any command negated to memr#, smemr#, memr#, smemw# asserted 28a memory access to 16-bit isa slave 3t cycles 28b memory access to 8-bit isa slave 3t cycles 28 any command negated to ior#, iow# asserted 28c i/o access to isa slave 3t cycles 29a memr#, memw# negated before next ale# asserted 1t cycles 29b smemr#, smemw# negated before next ale# asserted 1t cycles 29c ior#, iow# negated before next ale# asserted 1t cycles 33 la[23:17] valid to iochrdy negated 33a memory access to 16-bit isa slave - 4 bclk 8t cycles 33b memory access to 8-bit isa slave - 7 bclk 14t cycles 34 la[23:17] valid to read data valid 34b memory access to 16-bit isa slave standard cycle 8t cycles 34e memory access to 8-bit isa slave standard cycle 14t cycles 37 ale# asserted to iochrdy# negated 37a memory access to 16-bit isa slave - 4 bclk 6t cycles 37b memory access to 8-bit isa slave - 7 bclk 12t cycles 37c i/o access to 16-bit isa slave - 4 bclk 6t cycles 37d i/o access to 8-bit isa slave - 7 bclk 12t cycles 38 ale# asserted to read data valid 38b memory access to 16-bit isa slave standard cycle 4t cycles 38e memory access to 8-bit isa slave standard cycle 10t cycles 38h i/o access to 16-bit isa slave standard cycle 4t cycles 38l i/o access to 8-bit isa slave standard cycle 10t cycles table 4-14. isa bus ac timing name parameter min max units note: the si g nal numberin g refers to table 4-8
electrical specifications issue 1.0 - july 24, 2002 57/111 41 sa[19:0] sbhe valid to iochrdy negated 41a memory access to 16-bit isa slave 6t cycles 41b memory access to 8-bit isa slave 12t cycles 41c i/o access to 16-bit isa slave 6t cycles 41d i/o access to 8-bit isa slave 12t cycles 42 sa[19:0] sbhe valid to read data valid 42b memory access to 16-bit isa slave standard cycle 4t cycles 42e memory access to 8-bit isa slave standard cycle 10t cycles 42h i/o access to 16-bit isa slave standard cycle 4t cycles 42l i/o access to 8-bit isa slave standard cycle 10t cycles 47 memr#, memw#, smemr#, smemw#, ior#, iow# asserted to iochrdy negated 47a memory access to 16-bit isa slave 2t cycles 47b memory access to 8-bit isa slave 5t cycles 47c i/o access to 16-bit isa slave 2t cycles 47d i/o access to 8-bit isa slave 5t cycles 48 memr#, smemr#, ior# asserted to read data valid 48b memory access to 16-bit isa slave standard cycle 2t cycles 48e memory access to 8-bit isa slave standard cycle 5t cycles 48h i/o access to 16-bit isa slave standard cycle 2t cycles 48l i/o access to 8-bit isa slave standard cycle 5t cycles 54 iochrdy asserted to read data valid 54a memory access to 16-bit isa slave 1t(r)/2t(w) cycles 54b memory access to 8-bit isa slave 1t(r)/2t(w) cycles 54c i/o access to 16-bit isa slave 1t(r)/2t(w) cycles 54d i/o access to 8-bit isa slave 1t(r)/2t(w) cycles 55a iochrdy asserted to memr#, memw#, smemr#, smemw#, ior#, iow# negated 1t cycles 55b iochry asserted to memr#, smemr# negated (refresh) 1t cycles 56 iochrdy asserted to next ale# asserted 2t cycles 57 iochrdy asserted to sa[19:0], sbhe invalid 2t cycles 58 memr#, ior#, smemr# negated to read data invalid 0t cycles 59 memr#, ior#, smemr# negated to data bus float 0t cycles 61 write data before memw# asserted 61a memory access to 16-bit isa slave 2t cycles 61b memory access to 8-bit isa slave (byte copy at end of start) 2t cycles 61 write data before smemw# asserted 61c memory access to 16-bit isa slave 2t cycles 61d memory access to 8-bit isa slave 2t cycles 61 write data valid before iow# asserted 61e i/o access to 16-bit isa slave 2t cycles 61f i/o access to 8-bit isa slave 2t cycles 64a memw# negated to write data invalid - 16-bit 1t cycles 64b memw# negated to write data invalid - 8-bit 1t cycles 64c smemw# negated to write data invalid - 16-bit 1t cycles 64d smemw# negated to write data invalid - 8-bit 1t cycles table 4-14. isa bus ac timing name parameter min max units note: the signal numbering refers to table 4-8
electrical specifications 58/111 issue 1.0 - jul y 24, 2002 64e iow# negated to write data invalid 1t cycles 64f memw# negated to copy data float, 8-bit isa slave, odd byte by isa master 1t cycles 64g iow# negated to copy data float, 8-bit isa slave, odd byte by isa master 1t cycles table 4-14. isa bus ac timing name parameter min max units note: the si g nal numberin g refers to table 4-8
electrical specifications issue 1.0 - july 24, 2002 59/111 4.5.7 local bus interface figure 4-3 to figure 4-12 and table 4-16 list the ac characteristics of the local bus interface. figure 4-9. synchronous read cycle pa[ ] bus csx# be#[1:0] prd# hclk t setup t active t hold pd[15:0] figure 4-10. asynchronous read cycle pa[ ] bus csx# be#[1:0] prd# hclk t setup t end t hold pd[15:0] prdy
electrical specifications 60/111 issue 1.0 - jul y 24, 2002 figure 4-11. synchronous write cycle pa[ ] bus csx# be#[1:0] pwr# hclk t setup t active t hold pd[15:0] figure 4-12. asynchronous write cycle pa[ ] bus csx# be#[1:0] pwr# hclk t setup t end t hold prdy pd[15:0]
electrical specifications issue 1.0 - july 24, 2002 61/111 the table 4-15 below refers to vh, va, vs which are the register value for setup time, active time and hold time, as described in the programming manual. table 4-15. local bus cycle lenght cycle t setup t active t hold t end unit memory (fcsx#) 4 + vh 2 + va 4 + vs 4 hclk peripheral (iocsx#) 4 + vh 2 + va 4 + vs 4 hclk table 4-16. local bus interface ac timing name parameters min max units hclk to pa bus - 15 ns hclk to pd bus - 15 ns hclk to fcs#[1:0] - 15 ns hclk to iocs#[3:0] - 15 ns hclk to pwr#, prd# - 15 ns hclk to be#[1:0] - 15 ns pd[15:0] input setup to hclk - 4 ns pd[15:0] input hold to hclk 2 - ns prdy input setup to hclk - 4 ns prdy input hold to hclk 2 - ns
electrical specifications 62/111 issue 1.0 - jul y 24, 2002 4.5.8 pcmcia interface table 4-17 lists the ac characteristics of the pcmcia interface. table 4-17. pcmcia interface ac timing name parameters min max units t27 input setup to isaclk2x 24 ns t28 input hold from isaclk2x 5 ns t29 isaclk2x to iord - 55 ns t30 isaclk2x to iorw - 55 ns t31 isaclk2x to ad[25:0] - 25 ns t32 isaclk2x to oe# 2 55 ns t33 isaclk2x to we# 2 55 ns t34 isaclk2x to data[15:0] 0 35 ns t35 isaclk2x to inpack 2 55 ns t36 isaclk2x to ce1# 7 65 ns t37 isaclk2x to ce2# 7 65 ns t38 isaclk2x to reset 2 55 ns
electrical specifications issue 1.0 - july 24, 2002 63/111 4.5.9 ide interface figure 4-13 , figure 4-14 and table 4-18 lists the ac characteristics of the ide interface. figure 4-13. ide pio timing diagram figure 4-14. ide dma timing diagram dior#,diow# cs#,da[2:0] dd[15:0] t hold iordy t setup dior#,diow# cs# dd[15:0] read dd[15:0] write req ack# t hold t setup table 4-18. ide interface timing name parameters min max units tsetup dd[15:0] setup to pior#/sior# falling 15 - ns thold dd[15:0} hold to pior#/sior# falling 0 - ns
electrical specifications 64/111 issue 1.0 - jul y 24, 2002 4.5.10 vga interface table 4-19 lists the ac characteristics of the vga interface. 4.5.11 tft interface table 4-20 lists the ac characteristics of the tft interface. table 4-19. graphics adapter (vga) ac timing name parameter min max unit dclk (input) cycle time ns dclk (input) high time ns dclk (input) low time ns dclk (input) rising time ns dclk (input) falling time ns dclk (input) to r,g,b valid ns dclk (input) to hsync valid ns dclk (input) to vsync valid ns dclk (input) to col_sel valid ns dclk (output) cycle time ns dclk (output) high time ns dclk (output) low time ns dclk (output) to r,g,b valid ns dclk (output) to hsync valid ns dclk (output) to vsync valid ns dclk (output) to col_sel valid ns table 4-20. tft interface timings name parameters min max units dclk (input) to r[5:0], g[5:0], b[5;0] ns dclk (input) to fpline ns dclk (input) to fpframe ns dclk (output) to r[5:0], g[5:0], b[5;0] 15 ns dclk (output) to fpline 15 ns dclk (output) to fpframe 15 ns
electrical specifications issue 1.0 - july 24, 2002 65/111 4.5.12 video input port table 4-21 lists the ac characteristics of the vip interface. table 4-21. video input ac timings name parameter min max unit vclk cycle time ns vclk high time ns vclk low time ns vclk rising time ns vclk falling time ns vin[7:0] setup to vclk ns vin[7:0] hold from vclk ns odd_even setup to vclk ns odd_even hold from vclk ns vcs setup to vclk ns vcs hold from vclk ns
electrical specifications 66/111 issue 1.0 - jul y 24, 2002 4.5.13 usb interface the usb interface integrated into the stpc device is compliant with the usb 1.1 standard. 4.5.14 keyboard & mouse interfaces table 4-22 and table 4-23 list the ac characteristics of the keyboard and mouse interfaces. 4.5.15 ieee1284 interface table 4-24 lists the ac characteristics of the keyboard and mouse interfaces. table 4-22. keyboard interface ac timing name parameters min max units input setup to kbclk 5 - ns input hold to kbclk 1 - ns kbclk to kbdata - 12 ns table 4-23. mouse interface ac timing name parameters min max units input setup to mclk 5 - ns input hold to mclk 1 - ns mclk to mdata - 12 ns table 4-24. parallel interface ac timing name parameters min max units strobe# to busy setup 0 - ns pd bus to autpfd# hold 0 - ns pb bus to busy setup 0 - ns
electrical specifications issue 1.0 - july 24, 2002 67/111 4.5.16 jtag interface figure 4-15 and table 4-21 list the ac characteristics of the jtag interface. figure 4-15. jtag timing diagram table 4-25. jtag ac timings name parameter min max unit treset trst pulse width 1 tcycle tcycle tclk period 400 ns tclk rising time 20 ns tclk falling time 20 ns tjset tms setup time 200 ns tjhld tms hold time 200 ns tjset tdi setup time 200 ns tjhld tdi hold time 200 ns tjout tclk to tdo valid 30 ns tpset stpc pin setup time 30 ns tphld stpc pin hold time 30 ns tpout tclk to stpc pin valid 30 ns tck stpc.input trst t reset t cycle stpc.output tms,tdi tdo t jset t jhld t jout t pset t phld t pout
electrical specifications 68/111 issue 1.0 - jul y 24, 2002 4.5.17 intensionnally blank
mechanical data issue 1.0 - july 24, 2002 69/111 5. mechanical data 5.1. 516-pin package dimension the pin numbering for the stpc 516-pin plastic bga package is shown in figure 5-1 . dimensions are shown in figure 5-2 , table 5-1 and figure 5-3 , table 5-2 . figure 5-1. 516-pin pbga package - top view a b d e f g h j k l m n p r t u v w y aa ab ac ad ae af c 135791113151719212325 2 4 6 8 10 12 14 16 18 20 22 24 26 a b d e f g h j k l m n p r t u v w y aa ab ac ad ae af c 135791113151719212325 2468101214161820222426
mechanical data 70/111 issue 1.0 - jul y 24, 2002 figure 5-2. 516-pin pbga package - pcb dimensions table 5-1. 516-pin pbga package - pcb dimensions symbols mm inches min typ max min typ max a 34.80 35.00 35.20 1.370 1.378 1.386 b 1.22 1.27 1.32 0.048 0.050 0.052 c 0.60 0.76 0.90 0.024 0.030 0.035 d 1.57 1.62 1.67 0.062 0.064 0.066 e 0.15 0.20 0.25 0.006 0.008 0.001 f 0.05 0.10 0.15 0.002 0.004 0.006 g 0.75 0.80 0.85 0.030 0.032 0.034 a a b detail a1 ball pad corner d f e g c
mechanical data issue 1.0 - july 24, 2002 71/111 figure 5-3. 516-pin pbga package - dimensions table 5-2. 516-pin pbga package - dimensions symbols mm inches min typ max min typ max a 0.50 0.56 0.62 0.020 0.022 0.024 b 1.12 1.17 1.22 0.044 0.046 0.048 c 0.60 0.76 0.92 0.024 0.030 0.036 d 0.52 0.53 0.54 0.020 0.021 0.022 e 0.63 0.78 0.93 0.025 0.031 0.037 f 0.60 0.63 0.66 0.024 0.025 0.026 g 30.0 11.8 a b c solderball solderball after collapse d e f g
mechanical data 72/111 issue 1.0 - jul y 24, 2002 5.2. 516-pin package thermal data 516-pin pbga package has a power dissipation capability of 4.5w which increases to 6w when used with a heatsink. the structure in shown in fi g ure 5-4 . thermal dissipation options are illustrated in fi g ure 5-5 and fi g ure 5-6 . figure 5-4. 516-pin pbga structure thermal balls power & ground la y ers si g nal la y ers figure 5-5. thermal dissipation without heatsink ambient case junction board ambient ambient case junction board rca r j c r j b rba 66 125 8.5 rja = 13 c/w airflow = 0 board dimensions: the pbga is centred on board copper thickness: - 17m for internal layers - 34m for external layers - 10.2 cm x 12.7 cm - 4 layers (2 for signals, 1 gnd, 1vcc) there are no other devices 1 via pad per ground ball (8-mil wire) 40% copper on signal layers board temperature taken at the centre balls board
mechanical data issue 1.0 - july 24, 2002 73/111 figure 5-6. thermal dissipation with heatsink ambient case junction board ambient ambient case junction board rca rjc rjb rba 36 50 8.5 rja = 9.5 c/w airflow = 0 board dimensions: the pbga is centred on board copper thickness: - 17m for internal layers - 34m for external layers - 10.2 cm x 12.7 cm - 4 layers (2 for signals, 1 gnd, 1vcc) there are no other devices heat sink is 11.1c/w 1 via pad per ground ball (8-mil wire) 40% copper on signal layers board temperature taken at the centre balls board
mechanical data 74/111 issue 1.0 - jul y 24, 2002 5.3. soldering recommendations high quality, low defect soldering requires identifying the optimum temperature profile for reflowing the solder paste, therefore optimizing the process. the heating and cooling rise rates must be compatible with the solder paste and components. a typical profile consists of a preheat, dryout, reflow and cooling sections. the most critical parameter in the preheat section is to minimize the rate of temperature rise to less than 2 c / second, in order to minimize thermal shock on the semi-conductor components. dryout section is used primarily to ensure that the solder paste is fully dried before hitting reflow temperatures. solder reflow is accomplished in the reflow zone , where the solder paste is elevated to a temperature greater than the melting point of the solder. melting temperature must be exceeded by approximately 20 c to ensure quality reflow. in reality the profile is not a line, but rather a range of temperatures all solder joints must be exposed. the total temperature deviation from component thermal mismatch, oven loading and oven uniformity must be within the band. figure 5-7. reflow soldering temperature range temperature ( c ) time ( s ) preheat dryout reflow cooling 240 0 250 200 150 100 50 0
design guidelines issue 1.0 - july 24, 2002 75/111 6. design guidelines 6.1. typical applications the stpc atlas is well suited for many applications. some of the possible implementations are described below. 6.1.1. thin client a thin-client is a terminal running ica tm (citrix) or rdp tm (microsoft) protocol. the display is computed by the server and sent in a compressed way to the terminal for display. the same streaming approach is used for sending the keyboard/mouse/usb data to the server. these protocols have room for dedicated data channels in case the terminal is not thin and can execute locally some applications, hence optimizing the bandwidth usage. for example, if a terminal has browsing or mpeg decoding capability, the server will provide internet source files or mpeg streaming. the same hardware can run x-terminal protocol and can be reconfigured by the server when booting on the network by uploading a different os and application. figure 6-1. thin-client - block diagram stpc tft atlas sdram 64 flash lan audio kbd / mouse usb ieee1284 16 pci ide / pci vga mpeg decoder ccir
design guidelines 76/111 issue 1.0 - jul y 24, 2002 6.1.2. internet terminal the internet terminal described here is an optimized implementation where the stpc atlas board is integrated into the crt itself. the advantages are a reduced overall cost and a good image definition. the stpc atlas platform being integrated into the monitor itself enables the choice of a limited amount of horizontal frequencies and simplifies the crt driving stage: - 1024x768: 56.5khz horizontal, 70hz vertical - 800x600: 53.7khz horizontal, 85hz vertical like for the thin-client, an external mpeg decoder can be connected to the stpc atlas through the pci bus and the video input port. the same concept can be applied using a tft display instead of a crt. figure 6-2. internet terminal - block diagram h r,g,b tda9535 3 3 3 v booster yoke yoke tilt dc restoring quad dac 3 3 stpc e 2 prom stv2001 r,g,b hsync vsync atlas i 2 c key- key+ sel gpios sdram 64 flash modem audio kbd / mouse usb ieee1284 16 pci ide / pci rs232 smartcard
design guidelines issue 1.0 - july 24, 2002 77/111 6.2. stpc configuration the stpc is a very flexible product thanks to decoupled clock domains and to strap options enabling a user-optimized configuration. as some trade off are often necessary, it is important to do an analysis of the application needs prior to design a system based on this product. the applicative constraints are usually the following: - cpu performance - graphics / video performances - power consumption - pci bandwidth - booting time - emc some other elements can help to tune the choice: - code size of cpu consuming tasks - data size and location on the stpc side, the configurable parameters are the following: - synchronous / asynchronous mode - hclk speed - mclk speed - local bus / isa bus 6.2.1. local bus / isa bus the selection between the isa bus and the local bus is relatively simple. the first one is a standard bus but slow. the local bus is fast and programmable but doesn't support any dma nor external master mechanisms. the table 6-1 below summarize the selection: before implementing a function requiring dma capability on the isa bus, it is recommended to check if it exists on pci, or if it can be implemented differently, in order to use the local bus mode. 6.2.2. clock configuration the cpu clock and the memory clock are independent unless the "synchronous mode" strap option is set (see the strap options chapter). the potential clock configurations are then relatively limited as listed in table 6-2 . the advantage of the synchronous mode compared to the asynchronous mode is a lower latency when accessing sdram from the cpu or the pci (saves 4 mclk cycles for the first access of the burst). for the same cpu to memory transfer performance, mclk has to be roughly higher by 20mhz between sync and async modes to get the same system performance level (example: 66mhz sync = 86mhz async) . in all cases, use sdram with cas latency equals to 2 (cl2) for the best performances. the advantage of the asynchronous mode is the capability to reprogram the mclk speed on the fly. this could help for applications where power consumption must be optimized. the last, and more complex, information to consider is the behaviour of the software. in case high cpu or fpu computation is needed, it is sometime better to be in dx2-133/mclk=66 synchronous mode than dx2-133/mclk=90 asynchronous mode. this depends on the locality of the number crunching code and the amount of data manipulated. the table 6-3 below gives some examples. the right column correspond to the configuration number as described in table 6-2 : obviously, the values for hclk or mclk can be reduced compared to table 6-2 in case there is no need to push the device at its limits, or when avoiding to use specific frequency ranges (fm radio band for example). 6.3. architecture recommendations this section describes the recommend implementations for the stpc interfaces. for more details, download the reference schematics from the stpc web site. table 6-1. bus mode selection need selection legacy i/o device (floppy, ...), super i/o isa bus dma capability (soundblaster) isa bus flash, sram, basic i/o device local bus fast boot local bus boot flash of 4mb or more local bus programmable chip select local bus table 6-2. main stpc modes cmode hclk mhz cpu clock clock ratio mclk mhz 1 synchronous 66 133 (x2) 66 2 asynchronous 66 133 (x2) 90 table 6-3. clock mode selection constraints c need cpu power critical code fits into l1 cache 1 need cpu power code or data does not fit into l1 cache 3 need high pci bandwitdh 3 need flexible sdram speed 2
design guidelines 78/111 issue 1.0 - jul y 24, 2002 6.3.1. power decoupling an appropriate decoupling of the various stpc power pins is mandatory for optimum behaviour. when insufficient, the integrity of the signals is deteriorated, the stability of the system is reduced and emc is increased. 6.3.1.1. pll decoupling this is the most important as the stpc clocks are generated from a single 14mhz stage using multiple plls which are highly sensitive analog cells. the frequencies to filter are the 25-50 khz range which correspond to the internal loop bandwidth of the pll and the 10 to 100 mhz frequency of the output. pll power pins can be tied together to simplify the board layout. 6.3.1.2. decoupling of 3.3v and vcore a power plane for each of these supplies with one decoupling capacitance for each power pin is the minimum. the use of multiple capacitances with values in decade is the best (for example: 10pf, 1nf, 100nf, 10uf), the smallest value, the closest to the power pin. connecting the various digital power planes through capacitances will reduce furthermore the overall impedance and electrical noise. 6.3.2. 14mhz oscillator stage the 14.31818 mhz oscillator stage can be implemented using a quartz, which is the preferred and cheaper solution, or using an external 3.3v oscillator. the crystal must be used in its series-cut fundamental mode and not in overtone mode. it must have an equivalent series resistance (esr, sometimes referred to as rm) of less than 50 ohms (typically 8 ohms) and a shunt capacitance (co) of less than 7 pf. the balance capacitors of 16 pf must be added, one connected to each pin, as described in fi g ure 6-4 . in the event of an external oscillator providing the master clock signal to the stpc atlas device, the lvttl signal should be connected to xtali, as described in fi g ure 6-4 . as this clock is the reference for all the other on- chip generated clocks, it is strongly recommended to shield this stage , including the 2 wires going to the stpc balls, in order to reduce the jitter to the minimum and reach the optimum system stability. figure 6-3. pll decoupling vdd_pll vss_pll pwr 100nf 47uf gnd connections must be as short as possible figure 6-4. 14.31818 mhz stage 15pf 15pf xtalo xtali xtalo xtali 3.3v
design guidelines issue 1.0 - july 24, 2002 79/111 6.3.3. sdram the stpc provides all the signals for sdram control. up to 128 mbytes of main memory are supported. all banks must be 64 bits wide. up to 4 memory banks are available when using 16mbit devices. only up to 2 banks can be connected when using 64mbit and 128mbit components due to the reallocation of cs2# and cs3# signals. this is described in table 6-4 and table 6-5 . graphics memory resides at the beginning of bank 0. host memory begins at the top of graphics memory and extends to the top of populated sdram. bank 0 must always be populated. figure 6-5 , figure 6-6 and figure 6-7 show some typical implementations. the purpose of the serial resistors is to reduce signal oscillation and emi by filtering line reflections. the capacitance in figure 6-5 has a filtering effect too, while it is used for propagation delay compensation in the 2 other figures. figure 6-5. one memory bank with 4 chips (16-bit) cs0# ba[1:0] ma[12:0] we# ras0# dqm[7:0] mclki mclko dqm[7:6] reference knot cas0# md[63:48] dqm[5:4] md[47:32] dqm[3:2] md[31:16] dqm[1:0] md[15:0] md[63:0] mclka mclkb mclkc mclkd 10pf length(mclki) = length(mclky) with y = {a,b,c,d}
design guidelines 80/111 issue 1.0 - jul y 24, 2002 figure 6-6. one memory banks with 8 chips (8-bit) figure 6-7. two memory banks with 8 chips (8-bit) cs0# ba[1:0] ma[12:0] we# ras0# dqm[7:0] mclki mclko dqm[7] cas0# md[63:56] dqm[0] md[7:0] md[63:0] a 10pf length(mclki) = length(mclky) with y = {a,b,c,d,e,f,g,h} dqm[1] md[15:8] b c d e f g h cy2305 cs1# ba[1:0] ma[12:0] we# ras0# dqm[7:0] mclki mclko dqm[7] cas0# md[63:56] dqm[0] md[7:0] md[63:0] a 1 22pf length(mclki) = length(mclky x ) with dqm[1] md[15:8] b 1 c 1 d 1 e 1 f 1 g 1 h 1 cs0# a 0 b 0 c 0 d 0 e 0 f 0 g 0 h 0 x = {0,1} y = {a,b,c,d,e,f,g,h} cy2305
design guidelines issue 1.0 - july 24, 2002 81/111 for other implementations like 32-bit sdram devices, refers to the sdram controller signal multiplexing and address mapping described in the following table 6-4 and table 6-5 . 6.3.4. pci bus the pci bus is always active and the following control signals must be pulled-up to 3.3v or 5v through 2k2 resistors even if this bus is not connected to an external device: frame#, trdy#, irdy#, stop#, devsel#, lock#, serr#, perr#, pci_req#[2:0]. pci_clko must be connected to pci_clki through a 10 to 33 ohms resistor. figure 6-8 shows a typical implementation. for more information on layout constraints, go to the place and route recommendations section. table 6-4. dimm pinout sdram density 16 mbit 64/128 mbit 64/128 mbit stpc i/f internal banks 2 banks 2 banks 4 banks dimm pin number ... ma[10:0] ma[10:0] ma[10:0] ma[10:0] 123 - ma11 ma11 cs2# (ma11) 126 - ma12 - cs3# (ma12) 39 - - ba1 (ma12) cs3# (ba1) 122 ba0 (ma11) ba0 (ma13) ba0 (ma13) ba0 table 6-5. address mapping address mapping: 16 mbit - 2 internal banks stpc i/f ba0 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 ras address a11 a22 a21 a2 a19 a18 a17 a16 a15 a14 a13 a12 cas address a11 0 a24 a23 a10 a9 a8 a7 a6 a5 a4 a3 address mapping: 64/128 mbit - 2 internal banks stpc i/f ba0 ma12 ma11 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 ras address a11 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 cas addressa110 0 0 a26a25a10a9a8a7a6a5a4a3 address mapping: 64/128 mbit - 4 internal banks stpc i/f ba0 ba1 ma11 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 ras address a11 a12 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 cas address a11 a12 0 0 a26 a25 a10 a9 a8 a7 a6 a5 a4 a3 figure 6-8. typical pci clock routing pciclki pciclko pciclka pciclkb pciclkc 0 - 22 10 - 33 device a device b device c 0 - 33pf
design guidelines 82/111 issue 1.0 - jul y 24, 2002 in the case of higher clock load it is recommended to use a zero-delay clock buffer as described in fi g ure 6-9 . this approach is also recommended when implementing the delay on pciclki according to the pci section of the electrical specifications chapter. figure 6-9. pci clock routing with zero-delay clock buffer pciclki pciclko device a device b device c pll device d pciclki pciclko device a device b device c pll device d cy2305 cy2305 implementation 1 implementation 2
design guidelines issue 1.0 - july 24, 2002 83/111 6.3.5. local bus the local bus has all the signals to directly connect flash devices or i/o devices. figure 6-10 describes how to connect a 16-bit boot flash (the corresponding strap options must be set accordingly). figure 6-10. typical 16-bit boot flash implementation m58lw064a stpc 22 dq[15:0] a[22:1] ce oe w rp b clk rb le r 3v3 gnd reset# 16 pd[15:0] fcs0# pwr# sysrsti# prd# pa[22:1]
design guidelines 84/111 issue 1.0 - jul y 24, 2002 6.3.6. ipc most of the ipc signals are multiplexed: interrupt inputs, dma request inputs, dma acknowledge outputs. the fi g ure below describes a complete implementation of the irq[15:0] time-multiplexin g . when an interrupt line is used internally, the corresponding input can be grounded. in most of the embedded designs, only few interrupts lines are necessary and the glue logic can be simplified. when the interface is integrated into the stpc, the corresponding interrupt line can be grounded as it is connected internally. for example, if the integrated ide controller is activated, the irq[14] and irq[15] inputs can be grounded. figure 6-11. typical irq multiplexing 74x153 1c0 1y 1g irq[0] irq_mux[0] 1c1 1c2 1c3 2c0 2c1 2c2 2c3 a b 2g 2y irq_mux[1] irq[1] irq[2] irq[3] irq[4] irq[5] irq[6] irq[7] 74x153 1c0 1y 1g irq_mux[2] 1c1 1c2 1c3 2c0 2c1 2c2 2c3 a b 2g 2y irq_mux[3] irq[8] irq[9] irq[10] irq[11] irq[12] irq[13] irq[14] irq[15] isa_clk2x isa_clk timer 0 keyboard slave pic com2/com4 com1/com3 lpt2 lpt1 rtc mouse fpu pci / ide pci / ide floppy floppy
design guidelines issue 1.0 - july 24, 2002 85/111 the figure below describes a complete implementation of the external glue logic for dma request time-multiplexing and dma acknowledge demultiplexing. like for the interrupt lines, this logic can be simplified when only few dma channels are used in the application. this glue logic is not needed in local bus mode as it does not support dma transfers. figure 6-12. typical dma multiplexing and demultiplexing 74x153 1c0 1y 1g drq[0] dreq_mux[0] 1c1 1c2 1c3 2c0 2c1 2c2 2c3 a b 2g 2y dreq_mux[1] drq[1] drq[2] drq[3] drq[4] drq[5] drq[6] drq[7] 74x138 y0# a g2b dack0# y1# y2# y3# y4# y5# y6# y7# c b g2a isa_clk2x isa_clk isa, refresh isa, pio isa, fdc isa, pio slave dmac isa isa isa g1 dma_enc[0] dma_enc[1] dma_enc[2] dack1# dack2# dack3# dack5# dack6# dack7#
design guidelines 86/111 issue 1.0 - jul y 24, 2002 6.3.7. ide / isa dynamic demultiplexing some of the isa bus signals are dynamically multiplexed to optimize the pin count. fi g ure 6-13 describes how to implement the external g lue lo g ic to demultiplex the ide and isa interfaces. in local bus mode the two buffers are not needed and the nand gates can be simplified to inverters. 6.3.8. basic audio using ide interface when the application requires only basic audio capabilities, an audio dac on the ide interface can avoid using a pci-based audio device. this low cost solution is not cpu consuming thanks to the dma controller implemented in the ide controller and can generate 16-bit stereo sound. the clock speed is programmable when using the speaker output. figure 6-13. typical ide / isa demultiplexing master# 74xx245 rmrtccs# a b dir oe isaoe# kbcs# rtcrw# rtcds sa[19:8] stpc bus / dd[15:0] la[24] la[25] la[22] la[23] scs1# scs3# pcs1# pcs3# figure 6-14. basic audio on ide 74xx74 16 q q dd[15:0] d pr rst d[15:0] cs# pcs1 wr# a/b audio out right left stereo dac pdrq sysrsto# speaker pdiow# vcc vcc vcc stpc q q d pr rst note * : the inverter can be removed when the dac cs# is directly connected to gnd *
design guidelines issue 1.0 - july 24, 2002 87/111 6.3.9. vga interface the stpc integrates a voltage reference and video buffers. the amount of external devices is then limited to the minimum as described in the figure 6-15 . all the resistors and capacitors have to be as close as possible to the stpc while the circuit protector dalc112s1 must be close to the vga connector. the ddc[1:0] lines, not represented here, have also to be protected when they are used on the vga connector. col_sel can be used when implementing the picture-in-picture function outside the stpc, for example when multiplexing an analog video source. in that case, the crtc of the stpc has to be genlocked to this analog source. dclk is usually used by the tft display which has rgb inputs in order to synchronise the picture at the level of the pixel. when the vga interface is not needed, the signals r, g, b, hsync, vsync, comp, rset can be left unconnected, vss_dac and vdd_dac must then be connected to gnd. figure 6-15. typical vga implementation 143 vdd_dac comp vref_dac rset vss_dac 2.5v 10nf 100nf 47uf agnd col_sel dclk hsync vsync r g b 75 1% dalc112s1 agnd 3.3v 100nf 1%
design guidelines 88/111 issue 1.0 - jul y 24, 2002 6.3.10. usb interface the stpc integrates a usb host interface with a 2-port hub. the only external device needed are the esd protection circuits usbdf01w5 and a usb power supply controller. fi g ure 6-16 describes a typical implementation using these devices. figure 6-16. typical usb implementation note 1; the esd protection will be adequate for most applications. in some instances, problems ma y occur i f the devi ces on the usb chai n do not have enou g h power to drive the si g nal s adequatel y . we theref ore recommend that y ou replace the part with de- screte components and reduce the val ue of the capaci tor. poweron stpc tps2014 oc usbdmns[0] usbdpls[0] usbdmns[1] usbdpls[1] 5v connector gnd 9 10 11 12 1 2 6 7 3 4 8 5 100nf 2x 47uf 5 4 6,7,8 5v 2,3 1 usbvcc 100nf 5v tps2014 power decoupling r = 15 ohm 1 r = 15 ohm 1 r = 15 ohm 1 r = 15 ohm 1 usbdf02w5 (note1) 3 1 2 4 5 usbdf02w5 (note1) 3 1 2 4 5
design guidelines issue 1.0 - july 24, 2002 89/111 6.3.11. keyboard/mouse interface the stpc integrates a pc/at+ keyboard and ps/2 mouse controller. the only external devices needed are the esd protection circuits kbmf01sc6. figure 6-17 describes a typical implementation using a dual minidin connector. figure 6-17. typical keyboard / mouse implementation mdata mclk kbdata kbclk stpc 5v minidin gnd kbmf01sc6 4 13 3 7 8 9 12 16 17 5v kbmf01sc6 5v 10 14 1 5 2 6 11 15
design guidelines 90/111 issue 1.0 - jul y 24, 2002 6.3.12. parallel port interface the stpc integrates a parallel port where the only external device needed is the esd protection circuits st1284-01a8. fi g ure 6-18 describes a typical implementation using this device. figure 6-18. typical parallel port implementation ack# autofd# strobe# pd[7:0] stpc connector st1284-01a8 5v 8 8 busy pe slct slctin# init# err#
design guidelines issue 1.0 - july 24, 2002 91/111 6.3.13. jtag interface the stpc integrates a jtag interface for scan- chain and on-board testing. the only external device needed are the pull up resistors. figure 6- 19 describes a typical implementation using these devices. fi g ure 6-19. typical jtag implementation stpc tclk tdo 3v3 connector 9 10 1 2 6 7 3 4 8 5 tms tdi trst 3v3 3v3 3v3
design guidelines 92/111 issue 1.0 - jul y 24, 2002 6.4. place and route recommendations 6.4.1. general recommendations some stpc interfaces run at high speed and need to be carefully routed or even shielded like: 1) memory interface 2) pci bus 3) graphics and video interfaces 4) 14 mhz oscillator stage all clock signals have to be routed first and shielded for speeds of 27mhz or higher. the high speed signals follow the same constraints, as for the memory and pci control signals. the next interfaces to be routed are memory, pci, and video/graphics. all the analog noise-sensitive signals have to be routed in a separate area and hence can be routed indepedently. 6.4.2. pll definition and implimentation plls are analog cells which supply the internal stpc clocks. to get the cleanest clock, the jitter on the power supply must be reduced as much as possible. this will result in a more stable system. each of the integrated pll has a dedicated power pin so a single power plane for all of these plls, or one wire for each, or any solution in between which help the layout of the board can be used. powering these pins with one ferrite + capacitances is enough. we recommend at least 2 capacitances: one 'big' (few uf) for power storage, and one or 2 smalls (100nf + 1nf) for noise filtering. figure 6-20. shielding signals ground ring ground pad shielded signal line ground pad shielded signal lines
design guidelines issue 1.0 - july 24, 2002 93/111 6.4.3. memory interface 6.4.3.1. introduction in order to achieve sdram memory interfaces which work at clock frequencies of 90 mhz and above, careful consideration has to be given to the timing of the interface with all the various electrical and physical constraints taken into consideration. the guidelines described below are related to sdram components on dimm modules. for applications where the memories are directly soldered to the motherboard, the pcb should be laid out such that the trace lengths fit within the constraints shown here. the traces could be slightly shorter since the extra routing on the dimm pcb is no longer present but it is then up to the user to verify the timings. 6.4.3.2. sdram clocking scheme the sdram clocking scheme deserves a special mention here. basically the memory clock is generated on-chip through a pll and goes directly to the mclko output pin of the stpc. the nominal frequency is 90 mhz. because of the high load presented to the mclk on the board by the dimms it is recommended to rebuffer the mclko signal on the board and balance the skew to the clock ports of the different dimms and the mclki input pin of stpc. 6.4.3.3. board layout issues the physical layout of the motherboard pcb assumed in this presentation is as shown in figure 6-22 . because all of the memory interface signal balls are located in the same region of the stpc device, it is possible to orientate the device to reduce the trace lengths. the worst case routing length to the dimm1 is estimated to be 100 mm. solid power and ground planes are a must in order to provide good return paths for the signals and to reduce emi and noise. also there should be ample high frequency decoupling between the power and ground planes to provide a low impedance path between the planes for the return paths for signal routings which change layers. if possible, the traces should be routed adjacent to the same power or ground plane for the length of the trace. for the sdram interface, the most critical signal is the clock. any skew between the clocks at the sdram components and the memory controller will impact the timing budget. in order to get well matched clocks at all components it is recommended that all the dimm clock pins, stpc figure 6-21. clock scheme dimm1 mclki mclko dimm2 pll register pll ma[ ] + control md[63:0] sdram controller
design guidelines 94/111 issue 1.0 - jul y 24, 2002 memory clock input (mclki) and any other component using the memory clock are individually driven from a low skew clock driver with matched routing lengths. in other words, all clock line lengths that go from the buffer to the memory chips (mclkx) and from the buffer to the stpc (mclki) must be identical. this is shown in fi g ure 6-23 . figure 6-22. dimm placement dimm2 dimm1 stpc 35mm 35mm 15mm 10mm 116mm sdram i/f figure 6-23. clock routing mclko dimm ckn input stpc mclki dimm ckn input dimm ckn input low skew clock driver: l l+75mm* 20pf * no additional 75mm when sdram directly soldered on board
design guidelines issue 1.0 - july 24, 2002 95/111 the maximum skew between pins for this part is 250ps. the important factors for the clock buffer are a consistent drive strength and low skew between the outputs. the delay through the buffer is not important so it does not have to be a zero delay pll type buffer. the trace lengths from the clock driver to the dimm ckn pins should be matched exactly. since the propagation speed can vary between pcb layers, the clocks should be routed in a consistent way. the routing to the stpc memory input should be longer by 75 mm to compensate for the extra clock routing on the dimm. also a 20 pf capacitor should be placed as near as possible to the clock input of the stpc to compensate for the dimms higher clock load. the impedance of the trace used for the clock routing should be matched to the dimm clock trace impedance (60-75 ohms) . to minimise crosstalk the clocks should be routed with spacing to adjacent tracks of at least twice the clock trace width. for designs which use sdrams directly mounted on the motherboard pcb all the clock trace lengths should be matched exactly. the dimm sockets should be populated starting with the furthest dimm from the stpc device first (dimm1). there are two types of dimm devices; single-row and dual-row. the dual-row devices require two chip select signals to select between the two rows. a stpc device with 4 chip select control lines could control either 4 single-row dimms or 2 dual-row dimms. when only 2 chip select control lines are activated, only two single- row dimms or one dual-row dimm can be controlled. 6.4.3.4. summary for unbuffered dimms the address/control signals will be the most critical for timing. the simulations show that for these signals the best way to drive them is to use a parallel termination. for applications where speed is not so critical series termination can be used as this will save power. using a low impedance such as 50 w for these critical traces is recommended as it both reduces the delay and the overshoot. the other memory interface signals will typically be not as critical as the address/control signals. using lower impedance traces is also beneficial for the other signals but if their timing is not as critical as the address/control signals they could use the default value. using a lower impedance implies using wider traces which may have an impact on the routing of the board. the layout of this interface can be validated by an electrical simulation using the ibis model available on the stpc web site. 6.4.3.5. clock topology for on-board sdram figure 6-24 and figure 6-25 give the recommend- ed clock topology and the resulting ibis simulation in the case of four on-board sdram devices and no clock buffer. 6.4.3.6. clock topology for standard dimm figure 6-26 and figure 6-27 give the recommend- ed clock topology and the resulting ibis simulation in the case of a standard dimm with the use of a clock buffer. figure 6-24. recommended topology for 4 on-board sdrams (ibis model) mclki mclko 18 ohms 400 mils 3500 mils 3500 mils 3500 mils 3500 mils 400 mils mclk0 mclk1 mclk2 mclk3 track impedance= 75 ohms trace thickness = 0.72 mil trace width = 4 to 8 mils
design guidelines 96/111 issue 1.0 - jul y 24, 2002 figure 6-25. ibis simulation for on-board sdram / 90mhz figure 6-26. recommended topology for dimm (ibis model) 0.8 v 2.0 v 833ps 791ps 3 2 1 mclki mclkx (v) mclki time mclki 22 ohms 3000 mils track impedance= 75 ohms trace thickness = 0.72 mil trace width = 4 to 8 mils buffer out 18 ohms 2000 mils dimm buffer out
design guidelines issue 1.0 - july 24, 2002 97/111 figure 6-27. ibis simulation for dimm / 90mhz 3 2 1 (v) time 0.8 v 2.0 v buffer output mclki mclkx 1.40 ns 1.20 ns
design guidelines 98/111 issue 1.0 - jul y 24, 2002 6.4.4. pci interface 6.4.4.1. introduction in order to achieve a pci interface which work at clock frequencies up to 33mhz, careful consideration has to be given to the timing of the interface with all the various electrical and physical constraints taken into consideration. 6.4.4.2. pci clocking scheme the pci clocking scheme deserves a special mention here. basically the pci clock (pciclko) is generated on-chip from hclk through a programmable delay line and a clock divider. the nominal frequency is 33mhz. this clock must be looped to pciclki and goes to the internal south bridge through a deskewer. on the contrary, the internal north bridge is clocked by hclk, putting some additionnal constraints on t 0 and t 1 . figure 6-28. clock scheme hclk pll 1/2 1/3 1/4 clock strap options pciclko t 1 pciclki hclk ad[31:0] south north deskewer mux t 0 t 2 delay stpc md[30:27] md[17,4] md[7:6] bridge bridge
design guidelines issue 1.0 - july 24, 2002 99/111 6.4.4.3. board layout issues the physical layout of the motherboard pcb assumed in this presentation is as shown in figure 6-29 . for the pci interface, the most critical signal is the clock. any skew between the clocks at the pci components and the stpc will impact the timing budget. in order to get well matched clocks at all components it is recommended that all the pci clocks are individually driven from a serial resistance with matched routing lengths. in other words, all clock line lengths that go from the resistor to the pci chips (pciclkx) must be identical. the figure below is for pci devices soldered on- board. in the case of a pci slot, the wire length must be shortened by 2.5" to compensate the clock layout on the pci board. the maximum clock skew between all devices is 2ns according to pci specifications. the figure 6-30 describes a typical clock delay implementation. the exact timing constraints are listed in the pci section of the electrical specifications chapter. figure 6-29. typical pci clock routing length(pciclki) = length(pciclkx) with x = {a,b,c} note : the value of 22 ohms corresponds to tracks with z 0 = 70 ohms. pciclki pciclko pciclka pciclkb pciclkc device a device b device c figure 6-30. clocks relationships pciclko pciclki hclk pciclkx
design guidelines 100/111 issue 1.0 - jul y 24, 2002 6.4.5. thermal dissipation 6.4.5.1. power saving thermal dissipation of the stpc depends mainly on supply voltage. when the system does not need to work at the upper voltage limit, it may therefore be beneficial to reduce the voltage to the lower voltage limit, where possible. this could save a few 100s of mw. the second area to look at is unused interfaces and functions. depending on the application, some input signals can be grounded, and some blocks not powered or shutdown. clock speed dynamic adjustment is also a solution that can be used along with the integrated power management unit. 6.4.5.2. thermal balls the standard way to route thermal balls to ground layer implements only one via pad for each ball pad, connected using a 8-mil wire. with such configuration the plastic bga package does 90% of the thermal dissipation through the ground balls, and especially the central thermal balls which are directly connected to the die. the remaining 10% is dissipated through the case. adding a heat sink reduces this value to 85%. as a result, some basic rules must be followed when routing the stpc in order to avoid thermal problems. as the whole ground layer acts as a heat sink, the ground balls must be directly connected to it, as illustrated in fi g ure 6-31 . if one ground layer is not enough, a second ground plane may be added. when possible, it is important to avoid other devices on-board using the pcb for heat dissipation, like linear regulators, as this would heat the stpc itself and reduce the temperature range of the whole system, in case these devices can not use a separate heat sink, they must not be located just near the stpc figure 6-31. ground routing thru hole to ground layer t o p l a y e r : s i g n a l s p o w e r l a y e r i n t e r n a l l a y e r : s i g n a l s b o t t o m l a y e r : g r o u n d l a y e r pad for ground ball
design guidelines issue 1.0 - july 24, 2002 101/111 when considering thermal dissipation, one of the most important parts of the layout is the connection between the ground balls and the ground layer. a 1-wire connection is shown in figure 6-32 . the use of a 8-mil wire results in a thermal resistance of 105c/w assuming copper is used (418 w/ m.k). this high value is due to the thickness (34 m) of the copper on the external side of the pcb. considering only the central matrix of 36 thermal balls and one via for each ball, the global thermal resistance is 2.9c/w. this can be easily improved using four 12.5 mil wires to connect to the four vias around the ground pad link as in figure 6-33 . this gives a total of 49 vias and a global resistance for the 36 thermal balls of 0.5c/ w. the use of a ground plane like in figure 6-34 is even better. figure 6-32. recommended 1-wire power/ground pad layout solder mask (4 mil) pad for ground ball (diameter = 25 mil) hole to ground layer (diameter = 12 mil) connection wire (width = 12.5 mil) via (diameter = 24 mil) 3 4. 5 mil 1 mil = 0.0254 mm figure 6-33. recommended 4-wire ground pad layout 4 via pads for each ground ball
design guidelines 102/111 issue 1.0 - jul y 24, 2002 to avoid solder wicking over to the via pads during soldering, it is important to have a solder mask of 4 mil around the pad (nsmd pad). this gives a diameter of 33 mil for a 25 mil ground pad. to obtain the optimum ground layout, place the vias directly under the ball pads. in this case no local board distortion is tolerated. 6.4.5.3. heat dissipation the thickness of the copper on pcb layers is typically 34 m for external layers and 17 m for internal layers. this means that thermal dissipation is not good; high board temperatures are concentrated around the devices and these fall quickly with increased distance. where possible, place a metal layer inside the pcb; this improves dramatically the spread of heat and hence the thermal dissipation of the board. the possibility of using the whole system box for thermal dissipation is very useful in cases of high internal temperatures and low outside temperatures. bottom side of the pbga should be thermally connected to the metal chassis in order to propagate the heat flow through the metal. thermally connecting also the top side will improve furthermore the heat dissipation. fi g ure 6-35 illustrates such an implementation. figure 6-34. optimum layout for central ground ball - top layer via to ground layer pad for ground ball clearance = 6mil diameter = 25 mil hole diameter = 14 mil solder mask diameter = 33 mil external diameter = 37 mil connections = 10 mil figure 6-35. use of metal plate for thermal dissipation metal planes thermal conductor board die
design guidelines issue 1.0 - july 24, 2002 103/111 as the pcb acts as a heat sink, the layout of top and ground layers must be done with care to maximize the board surface dissipating the heat. the only limitation is the risk of losing routing channels. figure 6-36 and figure 6-37 show a routing with a good thermal dissipation thanks to an optimized placement of power and signal vias. the ground plane should be on bottom layer for the best heat spreading (thicker layer than internal ones) and dissipation (direct contact with air). . figure 6-36. layout for good thermal dissipation - top layer 1 a 3.3v ball 2.5v ball (core / plls) via stpc ball gnd ball not connected ball
design guidelines 104/111 issue 1.0 - jul y 24, 2002 figure 6-37. recommend signal wiring (top & ground layers) with corresponding heat flow power/gnd balls signal balls external row internal row gnd power power gnd power/gnd balls signal balls keep-out = 6 mils
design guidelines issue 1.0 - july 24, 2002 105/111 6.5. debug methodology in order to bring a stpc-based board to life with the best efficiency, it is recommended to follow the check-list described in this section. 6.5.1. power supplies in parallel with the assembly process, it is useful to get a bare pcb to check the potential short- circuits between the various power and ground planes. this test is also recommended when the first boards are back from assembly. this will avoid bad surprises in case of a short-circuit due to a bad soldering. when the system is powered, all power supplies, including the pll power pins must be checked to be sure the right level is present. see table 4-2 for the exact supported voltage range: vdd_core: 2.5v vdd_xxxpll: 2.5v vdd: 3.3v 6.5.2. boot sequence 6.5.2.1. reset input the checking of the reset sequence is the next step. the waveform of sysrsti# must complies with the timings described in figure 4-3 . this signal must not have glitches and must stay low until the 14.31818mhz output (osc14m) is at the right frequency and the strap options are stabilized to a valid configuration. in case this clock is not present, check the 14mhz oscillator stage (see figure 6-3 ). 6.5.2.2. strap options the stpc has been designed in a way to allow configurations for test purpose that differs from the functional configuration. in many cases, the troubleshootings at this stage of the debug are the resulting of bad strap options. this is why it is mandatory to check they are properly setup and sampled during the boot sequence. the list of all the strap options is summarized at the beginning of section 3. 6.5.2.3. clocks once osc14m is checked and correct, the next signals to measure are the host clock (hclk), pci clocks (pci_clko, pci_clki) and memory clock (mclko, mclki). hclk must run at the speed defined by the corresponding strap options (see table 3-1). in x2 cpu clock mode, this clock must be limited to 66mhz. pci_clki and pci_clko must be connected as described in figure 6-19 and not be higher than 33mhz. their speed depends on hclk and on the divider ratio defined by the md[4] and md[17] strap options as described in section 3. to ensure a correct behaviour of the device, the pci deskewing logic must be configured properly by the md[7:6] strap options according to section 3. for timings constraints, refers to section 4. 1) mclki and mclko must be connected as described in figure 6-3 to figure 6-5 depending on the sdram implementation. the memory clock must run at hclk speed when in synchronous mode and must not be higher than 90mhz in any case. the mclk interface will run 100mhz operation is possible but board layout is so critical that 90mhz maximum operation is recommended. 6.5.2.4. reset output if sysrsti# and all clocks are correct, then the sysrsto# output signal should behave as described in figure 4-3 . 6.5.3. isa mode prior to check the isa bus control signals, pci_clki, isa_clk, isa_clk2x, and dev_clk must be running properly. if it is not the case, it is probably because one of the previous steps has not been completed. 6.5.3.1. first code fetches when booting on the isa bus, the two key signals to check at the very beginning are rmrtccs# and frame#. the first one is a chip select for the boot flash and is multiplexed with the ide interface. it should toggle together with isaoe# and memrd# to fetch the first 16 bytes of code. this corresponds to the loading of the first line of the cpu cache. in case rmrtccs# does not toggle, it is then necessary to check the pci frame# signal. indeed the isa controller is part of the south bridge and all isa bus cycles are visible on the pci bus. if there is no activity on the pci bus, then one of the previous steps has not been checked properly. if there is activity then there must be something conflicting on the isa bus or on the pci bus.
design guidelines 106/111 issue 1.0 - jul y 24, 2002 6.5.3.2. boot flash size the isa bus supports 8-bit and 16-bit memory devices. in case of a 16-bit boot flash, the signal memcs16# must be activated during rmrtccs# cycle to inform the isa controller of a 16-bit device. 6.5.3.3. post code once the 16 first bytes are fetched and decoded, the cpu core continue its execution depending on the content of these first data. usually, it corresponds to a jump instruction and the code fetching continues, generating read cycles on the isa bus. most of the bios and boot loaders are reading the content of the flash, decompressing it in sdram, and then continue the execution by jumping to the entry point in ram. this boot process ends with a jump to the entry point of the os launcher. these various steps of the booting sequence are codified by the so-called post codes (power-on self-test). a 8-bit code is written to the port 80h at the beginning of each stage of the booting process (i/o write to address 0080h) and can be displayed on two 7-segment display, enabling a fast visual check of the booting completion level. usually, the last post code is 0x00 and corresponds to the jump into the os launcher. when the execution fails or hangs, the lastest written code stays visible on that display, indicating either the piece of code to analyse, either the area of the hardware not working properly. 6.5.4. local bus mode as the local bus controller is located into the host interface, there is no access to the cycles on the pci, reducing the amount of signals to check. 6.5.4.1. first code fetches when booting on the local bus, the key signal to check at the very beginning is fcs0#. this signal is a chip select for the boot flash and should toggle together with prd# to fetch the first 16 bytes of code. this corresponds to the loading of the first line of the cpu cache. in case fcs0# does not toggle, then one of the previous steps has not been done properly, like hclk speed and cpu clock multiplier (x1, x2). 6.5.4.2. boot flash size the local bus support 16-bit boot memory devices only. 6.5.4.3. post code like in isa mode, post codes can be implemented on the local bus. the difference is that an iocs# must be programmed at i/o address 80h prior to writing these code, the post display being connected to this iocs# and to the lower 8 bits of the bus. 6.5.5. summary here is a check-list for the stpc board debug from power-on to cpu execution. for each step, in case of failure, verify first the corresponding balls of the stpc: - check if the voltage or activity is correct - search for potential shortcuts. for troubleshooting in steps 5 to 10, verify the related strap options: - value & connection. refer to section 3. - see fi g ure 4-3 for timing constraints steps 8a and 9a are for debug in isa mode while steps 8b and 9b are for local bus mode. 6.5.6. pcmcia mode as the stpc uses the rmrtccs# si g nal for bootin g in that mode, the methodolo g y is the same as for the isa bus. the pcmcia cards bein g 3.3v or 5v, the boot flash device must be 5v tolerant when directly connected on the address and data busses. an other solution is to isolate the flash from the pcmcia lines usin g 5v tolerant lvttl buffers. check: how? troubleshooting 1 power supplies verify that voltage is within specs: - this must include hf & lf noise - avoid full range sweep refer to table 4-1 for values measure voltage near stpc balls: - use very low gnd connection. add some decoupling capacitor: - the smallest, the nearest to stpc balls. 2 14.318 mhz verify osc14m speed the 2 capacitors used with the quartz must match with the capacitance of the crystal. try other values.
design guidelines issue 1.0 - july 24, 2002 107/111 3 sysrsti# (power good) measure sysrsti# of stpc see figure 4-3 for waveforms. verify reset generation circuit: - device reference - components value 5 hclk measure hclk is at selected frequency 25mhz < hclk < 66mhz hclk wire must be as short as possible 6 pci clocks measure pciclko: - maximum is 33mhz by standard - check it is at selected frequency - it is generated from hclk by a division (1/2, 1/3 or 1/4) check pciclki equals pciclko verify pciclko loops to pciclki. verify maximum skew between any pci clock branch is below 2ns. in synchronous mode, check mclki. 7 memory clocks measure mclko: - use a low-capacitance probe - maximum is 90mhz - check it is at selected frequency - in sync mode mclk=hclk - in async mode, default is 66mhz check mclki equals mclko verify load on mclki. verify mclk programming (bios setting). 4 sysrsto# measure sysrsto# of stpc see figure 4-3 for waveforms. verify sysrsti# duration. verify sysrsti# has no glitch verify clocks are running. 8a pci cycles check pci signals are toggling: - frame#, irdy#, trdy#, devsel# - these signals are active low. check, with a logic analyzer, that first pci cycles are the expected ones: memory read starting at address with lower bits to 0xfff0 verify pci slots if the stpc dont boot - verify data read from boot memory is ok - ensure flash is correctly programmed - ensure cmos is cleared. 9a isa cycles to boot memory check rmrtccs# & memrd# check directly on boot memory pin verify memcs16#: - must not be asserted for 8-bit memory verify iochrdy is not be asserted verify isaoe# pin: - it controls ide / isa bus demultiplexing 8b local bus cycles to boot memory check fcs0# & prd# check directly on boot memory pin verify hclk speed and cpu clock mode. 9b check, with a logic analyzer, that first local bus cycles are the expected one: memory read starting at the top of boot memory less 16 bytes if the stpc dont boot - verify data read from boot memory is ok - ensure flash is correctly programmed - ensure cmos is cleared. 10 the cpu fills its first cache line by fetching 16 bytes from boot memory. then, first instructions are executed from the cpu. any boot memory access done after the first 16 bytes are due to the instructions executed by the cpu => minimum hardware is correctly set, cpu executes code. please have a look to the bios writers guide or programming manual to go further with your board testing. check: how? troubleshooting
design guidelines 108/111 issue 1.0 - jul y 24, 2002 6.5.7.
ordering data issue 1.0 - july 24, 2002 109/111 7. ordering data 7.1. ordering codes st pc i2 h e y c stmicroelectronics prefix product family pc: pc compatible product id i2: atlas core speed g: 120 mhz h: 133 mhz memory speed d: 90 mhz e: 100 mhz package y: 516 overmoulded bga temperature range c: commercial tcase = 0 to +85c i: industrial tcase = -40 to +115c
ordering data 110/111 issue 1.0 - jul y 24, 2002 7.2. available part numbers part number core frequency (mhz) cpu mode memory interface speed (mhz) tcase range (c) operating voltage (v) stpci2heyc 1 133 x2 90 0c to +85c 2.45 - 2.7 3.0 - 3.6 stpci2gdyi 120 x2 90 -40c to +115c note 1: the stpc atlas mclock signal can run up to 100mhz reliably, but pcb layout is so critical that the maximum guaranteed speed is 90mhz
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. ? 2000 stmicroelectronics - all rights reserved the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. stmicroelectronics group of companies australia - brazil - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. 111 issue 1.0

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